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| m68hc08 microcontrollers freescale.com 68hc08tv24 68hc908tv24 advance information rev. 2.1 mc68hc908tv24/d august 16, 2005
mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor list of sections 3 advance information ? mc68hc908tv24 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 29 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 3. low-power modes . . . . . . . . . . . . . . . . . . . . . 57 section 4. resets and in terrupts . . . . . . . . . . . . . . . . . . . 67 section 5. analog-to-digital converter (adc4) . . . . . . 81 section 6. break module (brk). . . . . . . . . . . . . . . . . . . . 87 section 7. clock generator module (cgmc) . . . . . . . 97 section 8. closed-caption data slicer (dsl) . . . . . . . 127 section 9. configuration regist er (config). . . . . . . . 143 section 10. computer operating properly (cop) . . . 147 section 11. central processor un it (cpu) . . . . . . . . . . 153 section 12. user flash memory . . . . . . . . . . . . . . . . . . 171 section 13. on-screen display (osd) flash memory . . . . . . . . . . . . . . . . . . . . 185 section 14. external interrupt (irq ) . . . . . . . . . . . . . . . 195 section 15. low-voltage inhibit (l vi). . . . . . . . . . . . . . 201 section 16. monitor rom (mon) . . . . . . . . . . . . . . . . . 207 section 17. on-screen display module (osd) . . . . . . 221 advance information mc68hc908tv24 ? rev. 2.1 4 list of sections freescale semiconductor list of sections section 18. input/output (i/o) port s . . . . . . . . . . . . . . 267 section 19. random-access me mory (ram) . . . . . . . 277 section 20. system integratio n module (sim) . . . . . . . 279 section 21. serial synchronous interface module (ssi) . . . . . . . . . . . . . . . . . . . . . . . 305 section 22. timebase module (tbm) . . . . . . . . . . . . . . 319 section 23. timer interface modul e (tim) . . . . . . . . . . 325 section 24. rom version overvi ew (rom) . . . . . . . . . 349 section 25. preliminary electri cal specifications . . . . 353 section 26. mechanical specifications . . . . . . . . . . . . 363 section 27. ordering information. . . . . . . . . . . . . . . . . 365 mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 5 advance information ? mc68hc908tv24 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3.1 standard features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3.2 television applicati on-specific features . . . . . . . . . . . . . . . 32 1.3.3 cpu08 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 36 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 37 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.5 cgm power supply pins (v ddcgm and v sscgm ) . . . . . . . . 37 1.6.6 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 37 1.6.7 power supply pin s for on-screen display (v ddosd and v ssosd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.8 external filter pins for on-screen display (osdvco and osdpmp) . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.9 synchronism signals (hsync and vsync) . . . . . . . . . . . . 38 1.6.10 color encoded pixel signals (r, g, b, and i). . . . . . . . . . . . 38 1.6.11 fast blanking signal (fbkg) . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.12 serial synchronous interface clocks (scl1 and scl2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.13 serial synchronous interface data lines (sda1 and sda2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.14 video input (video ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.15 a/d converter input ( adcin) . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.16 timer i/o pins (tch1 and tch0) . . . . . . . . . . . . . . . . . . . . 39 advance information mc68hc908tv24 ? rev. 2.1 6 table of contents freescale semiconductor table of contents 1.6.17 timer external clock input (tclk) . . . . . . . . . . . . . . . . . . . 39 1.6.18 port a i/o pins (pta7?p ta0) . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.19 port b i/o pins (ptb7?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.20 port c i/o pins (ptc4?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 40 1.6.21 scan enable (scanen). . . . . . . . . . . . . . . . . . . . . . . . . . . .40 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 section 3. low-power modes 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.3 a/d converter (adc4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.4 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.5 central processor unit ( cpu). . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.6 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.7 closed-caption data slicer module ( dsl) . . . . . . . . . . . . . . . . 61 3.8 computer operating prop erly module (cop). . . . . . . . . . . . . . 61 3.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 7 3.9 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . .61 3.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.10 low-voltage inhibit module (lvi) . . . . . . . . . . . . . . . . . . . . . . . 62 3.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.11 on-screen display module (osd) . . . . . . . . . . . . . . . . . . . . . . 62 3.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.12 serial synchronous interface module (ssi) . . . . . . . . . . . . . . . 63 3.13 timer interface module (t im) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.14 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.14.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.14.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.15 exiting wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.16 exiting stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 section 4. resets and interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.3 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.4 system integration module (sim ) reset status register. . . 71 4.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.2 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.3 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 advance information mc68hc908tv24 ? rev. 2.1 8 table of contents freescale semiconductor table of contents section 5. analog-to-digital converter (adc4) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3 feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.2 conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.3 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6 adc control and status register . . . . . . . . . . . . . . . . . . . . . . . 84 5.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 6. break module (brk) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . . 90 6.4.2 cpu during break interr upts . . . . . . . . . . . . . . . . . . . . . . . .90 6.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.4 cop during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.6.1 break status and control register. . . . . . . . . . . . . . . . . . . . 92 6.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.6.3 sim break status regist er . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . . 95 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 9 section 7. clock generator module (cgmc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 101 7.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . 102 7.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . 103 7.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . . 108 7.4.8 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4.9 cgmc external connections . . . . . . . . . . . . . . . . . . . . . . . 109 7.5 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 110 7.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 110 7.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 111 7.5.4 pll analog power pin (v ddcgm ). . . . . . . . . . . . . . . . . . . .111 7.5.5 pll anal og ground pin (v sscgm ) . . . . . . . . . . . . . . . . . . . 111 7.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 111 7.5.7 cgmc base clock output (cgmou t) . . . . . . . . . . . . . . . 112 7.5.8 cgmc cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . 112 7.6 cgmc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .117 7.6.3 pll multiplier select register high . . . . . . . . . . . . . . . . . . 118 7.6.4 pll multiplier select register low. . . . . . . . . . . . . . . . . . . 119 7.6.5 pll vco range select register . . . . . . . . . . . . . . . . . . . .120 7.6.6 pll reference divider select register . . . . . . . . . . . . . . . 121 7.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 7.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 7.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 7.8.3 cgmc during break inte rrupts . . . . . . . . . . . . . . . . . . . . . 123 7.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 123 advance information mc68hc908tv24 ? rev. 2.1 10 table of contents freescale semiconductor table of contents 7.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .124 7.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 124 7.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 section 8. closed-capti on data slicer (dsl) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 8.4.1 slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.4.2 line and field de tection. . . . . . . . . . . . . . . . . . . . . . . . . . .129 8.4.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.2 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.3 debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 8.6 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.6.1 video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.6.2 vsync, hsync, and video input require ments . . . . . . . 132 8.7 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.7.1 dsl character registers . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.7.2 dsl control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.7.3 dsl control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.7.4 dsl status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.9 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 section 9. configurat ion register (config) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 11 section 10. computer op erating properly (cop) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 150 10.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 152 section 11. central processor unit (cpu) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.5 arithmetic/logic unit (alu ) . . . . . . . . . . . . . . . . . . . . . . . . . . 161 advance information mc68hc908tv24 ? rev. 2.1 12 table of contents freescale semiconductor table of contents 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 11.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 section 12. user flash memory 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.5 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.5.1 flash charge pump frequency control . . . . . . . . . . . . . 175 12.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . 178 12.8 user flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . 181 12.9 user flash block protect register . . . . . . . . . . . . . . . . . . . .182 12.10 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.11 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 section 13. on-scr een display (osd) flash memory 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 13.4 osd flash control register . . . . . . . . . . . . . . . . . . . . . . . . 187 13.5 charge pump frequency c ontrol . . . . . . . . . . . . . . . . . . . . . . 189 13.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . 192 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 13 13.8 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.9 osd flash block protect register. . . . . . . . . . . . . . . . . . . .193 section 14. external interrupt (irq) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 14.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 199 14.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 199 section 15. low-volt age inhibit (lvi) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 15.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .204 15.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 204 15.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 15.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 15.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 15.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 advance information mc68hc908tv24 ? rev. 2.1 14 table of contents freescale semiconductor table of contents section 16. monitor rom (mon) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 16.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 16.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.4.6 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 section 17. on-screen display module (osd) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 17.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 17.4.1 single-row architecture . . . . . . . . . . . . . . . . . . . . . . . . . . .225 17.4.2 display timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 17.4.3 registers and pixel memo ry . . . . . . . . . . . . . . . . . . . . . . .226 17.4.4 osd output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.5 display characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.1 closed-caption mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2 on-screen display mode . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.6 flash programming guideli nes . . . . . . . . . . . . . . . . . . . . . . 234 17.7 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.7.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.7.2 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.7.3 software controlled feat ures. . . . . . . . . . . . . . . . . . . . . . . 242 17.8 input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.8.1 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.2 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.3 pll filter pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.4 output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 15 17.9 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.9.1 osd character registers. . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.9.2 osd vertical delay r egister . . . . . . . . . . . . . . . . . . . . . . .251 17.9.3 osd horizontal delay register . . . . . . . . . . . . . . . . . . . . . 252 17.9.4 osd foreground control register . . . . . . . . . . . . . . . . . . . 252 17.9.5 osd background control register . . . . . . . . . . . . . . . . . . 254 17.9.6 osd border control re gister. . . . . . . . . . . . . . . . . . . . . . . 255 17.9.7 osd enable control register . . . . . . . . . . . . . . . . . . . . . . 257 17.9.8 osd event line register . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.9.9 osd event count regist er . . . . . . . . . . . . . . . . . . . . . . . . 260 17.9.10 osd output control re gister. . . . . . . . . . . . . . . . . . . . . . . 260 17.9.11 osd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 17.9.12 osd matrix start regist er . . . . . . . . . . . . . . . . . . . . . . . . . 263 17.9.13 osd matrix end regist er . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 17.11 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 section 18. input/output (i/o) ports 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 18.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 270 18.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 275 advance information mc68hc908tv24 ? rev. 2.1 16 table of contents freescale semiconductor table of contents section 19. random-a ccess memory (ram) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 section 20. system inte gration module (sim) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 20.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 283 20.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . 284 20.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 284 20.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 284 20.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 286 20.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 289 20.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 290 20.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 290 20.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 20.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 20.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 20.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 20.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 296 20.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 20.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 20.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.8.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 301 20.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . .303 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 17 section 21. serial synchronous interface module (ssi) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 21.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 21.4.1 start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 21.4.2 slave address transmission . . . . . . . . . . . . . . . . . . . . . . .309 21.4.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 21.4.4 stop signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.5 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.6 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.7 clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5.2 interrupt serving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 21.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 21.6.1 ssi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 21.6.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 21.6.3 ssi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 21.8 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 section 22. timebase module (tbm) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 22.5 timebase register description. . . . . . . . . . . . . . . . . . . . . . . . 321 22.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 22.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 advance information mc68hc908tv24 ? rev. 2.1 18 table of contents freescale semiconductor table of contents section 23. timer interface module (tim) 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 23.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.4 unbuffered output com pare . . . . . . . . . . . . . . . . . . . . . . .330 23.4.5 buffered output compar e . . . . . . . . . . . . . . . . . . . . . . . . . 330 23.4.6 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 331 23.4.7 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . 332 23.4.8 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . 333 23.4.9 pwm initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 23.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 23.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 23.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 336 23.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 23.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 23.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 337 23.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.9.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 341 23.9.4 tim channel status and control registers . . . . . . . . . . . . 342 23.9.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 section 24. rom version overview (rom) 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.3 flash for rom substitution . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.4 configuration register programming . . . . . . . . . . . . . . . . . . . 351 table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor table of contents 19 section 25. preliminary el ectrical specifications 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 25.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 354 25.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 355 25.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 25.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 356 25.7 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 25.8 adc4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 25.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 359 25.10 clock generation module characteristics . . . . . . . . . . . . . . . 359 25.10.1 cgm component specifications . . . . . . . . . . . . . . . . . . . . 359 25.10.2 cgm electrical specif ications . . . . . . . . . . . . . . . . . . . . . . 360 25.11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 25.12 5.0-v ssi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 section 26. mechanic al specifications 26.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 26.3 52-pin plastic quad flat pack (pqfp). . . . . . . . . . . . . . . . . . 364 section 27. ordering information 27.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 27.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 27.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 advance information mc68hc908tv24 ? rev. 2.1 20 table of contents freescale semiconductor table of contents mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor list of figures 21 advance information ? mc68hc908tv24 list of figures figure title page 1-1 mc68hc908tv24 block diagr am . . . . . . . . . . . . . . . . . . . . 34 1-2 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2-2 control, status, and data registers. . . . . . . . . . . . . . . . . . . 45 4-1 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4-2 power-on reset recovery. . . . . . . . . . . . . . . . . . . . . . . . . . 70 4-3 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . 72 4-4 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4-5 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . 74 4-6 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4-7 interrupt status regist er 1 (int1) . . . . . . . . . . . . . . . . . . . . 80 4-8 interrupt status regist er 2 (int2) . . . . . . . . . . . . . . . . . . . . 80 5-1 adc4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5-2 adc conversion code example . . . . . . . . . . . . . . . . . . . . . 83 5-3 adc control and status register (adccsr) . . . . . . . . . . . 84 6-1 break module block diagr am. . . . . . . . . . . . . . . . . . . . . . . . 89 6-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6-3 break status and control register (brkscr) . . . . . . . . . . 92 6-4 break address register high (brkh) . . . . . . . . . . . . . . . . . 93 6-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . 93 6-7 example code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6-6 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . . 94 6-8 sim break flag control register (sbfcr) . . . . . . . . . . . . . 95 list of figures advance information mc68hc908tv24 ? rev. 2.1 22 list of figures freescale semiconductor figure title page 7-1 cgmc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7-2 cgmc exernal connections . . . . . . . . . . . . . . . . . . . . . . .110 7-3 cgmc i/o register summary . . . . . . . . . . . . . . . . . . . . . . 113 7-4 pll control register (p ctl) . . . . . . . . . . . . . . . . . . . . . . . 114 7-5 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 117 7-6 pll multiplier select register high (pmsh) . . . . . . . . . . . 118 7-7 pll multiplier select register low (pmsl) . . . . . . . . . . . . 119 7-8 pll vco range select register (pmrs) . . . . . . . . . . . . . 120 7-9 pll reference divider select register (pmds) . . . . . . . . 121 7-10 pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8-1 data slicer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 129 8-2 slicer input and output. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8-3 video input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8-4 dsl input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8-5 dsl character registers ( dslch1 and dslch2) . . . . . . 135 8-6 dsl control register 1 (dslcr1). . . . . . . . . . . . . . . . . . . 136 8-7 dsl control register 2 (dslcr2). . . . . . . . . . . . . . . . . . . 138 8-8 data and sync slicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8-9 conditions for setting vertical pu lse delay . . . . . . . . . . . . 140 8-10 dsl status register (dslsr) . . . . . . . . . . . . . . . . . . . . . . 141 9-1 configuration register (config) . . . . . . . . . . . . . . . . . . . 144 10-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10-2 cop control register (copctl). . . . . . . . . . . . . . . . . . . .150 11-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11-3 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . 159 12-1 user flash control register (fl1c r) . . . . . . . . . . . . . . . 173 12-2 smart programming algorithm flow chart . . . . . . . . . . . . . 180 list of figures mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor list of figures 23 figure title page 12-3 user flash block protect regist er (fl1bpr) . . . . . . . . . 182 13-1 connection of the o sd flash memory . . . . . . . . . . . . . . 186 13-2 flash control register (fl2cr) . . . . . . . . . . . . . . . . . . . 187 13-3 osd flash block protect regist er (fl2bpr) . . . . . . . . . 193 14-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . 197 14-2 irq i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . 197 14-3 irq status and cont rol register (intscr) . . . . . . . . . . . . 200 15-1 lvi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 203 15-2 lvi i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 203 15-3 lvi status register (l visr). . . . . . . . . . . . . . . . . . . . . . . . 205 16-1 monitor mode circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16-2 monitor data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . 212 16-4 break transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16-6 read (read memory) command . . . . . . . . . . . . . . . . . . . 215 16-7 write (write memory) command . . . . . . . . . . . . . . . . . . 215 16-8 iread (indexed read) command . . . . . . . . . . . . . . . . . . . 216 16-9 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . 216 16-10 readsp (read stack pointer) command. . . . . . . . . . . . . 217 16-11 run (run user program) command. . . . . . . . . . . . . . . . . 217 16-12 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . 218 17-1 osd block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17-2 active display area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 17-3 cc-rom pixel matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17-4 boundary conditions with italics . . . . . . . . . . . . . . . . . . . . 230 17-5 osd-rom pixel matrix with no rthwest shadow . . . . . . . . 231 17-6 example of 3d shadow . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 17-7 behavior of control characters in osd mode . . . . . . . . . . 232 17-8 overlaying characters to get two foreground colors . . . 233 17-9 osd flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . 234 list of figures advance information mc68hc908tv24 ? rev. 2.1 24 list of figures freescale semiconductor figure title page 17-10 osd pixel matrix in flash memory . . . . . . . . . . . . . . . . . 235 17-11 cc pixel matrix in flash memory . . . . . . . . . . . . . . . . . . 236 17-12 spaces and box-making characte rs in cc mode . . . . . . . 237 17-13 pixel matrices organization in fl ash . . . . . . . . . . . . . . . . 238 17-14 pll filter circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17-15 osd character register s (osdchar1?osdchar34) . . 245 17-16 cc mode contro l character ? forma t a . . . . . . . . . . . . . 246 17-17 cc mode contro l character ? forma t b . . . . . . . . . . . . . 246 17-18 cc mode contro l character ? forma t c . . . . . . . . . . . . . 246 17-19 osd mode control character ? format a . . . . . . . . . . . . 248 17-20 osd mode control character ? format b . . . . . . . . . . . . 248 17-21 osd mode control character ? format c . . . . . . . . . . . . 248 17-22 osd vertical delay register (o sdvdr) . . . . . . . . . . . . . . 251 17-23 osd horizontal delay register (osdhdr). . . . . . . . . . . . 252 17-24 osd foreground contro l register (osdfcr) . . . . . . . . . 253 17-25 osd background control regist er (osdbkcr) . . . . . . . . 254 17-26 osd border control register (o sdbcr) . . . . . . . . . . . . . 255 17-27 osd enable control r egister (osdectr) . . . . . . . . . . . . 257 17-28 osd event line regist er (osdelr) . . . . . . . . . . . . . . . . . 259 17-29 osd event count register (osdecr) . . . . . . . . . . . . . . . 260 17-30 osd output control register (osdocr) . . . . . . . . . . . . . 260 17-31 osd status register (osdsr) . . . . . . . . . . . . . . . . . . . . . 262 17-32 osd matrix start regi ster (osdmsr). . . . . . . . . . . . . . . . 264 17-33 osd matrix end regist er (osdmer) . . . . . . . . . . . . . . . . 265 18-1 i/o port register summary . . . . . . . . . . . . . . . . . . . . . . . . 268 18-2 port a data register (p ta) . . . . . . . . . . . . . . . . . . . . . . . . 269 18-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 270 18-4 port a i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18-5 port b data register (p tb) . . . . . . . . . . . . . . . . . . . . . . . . 272 18-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 273 18-7 port b i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18-8 port c data register (p tc) . . . . . . . . . . . . . . . . . . . . . . . . 274 18-9 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 275 18-10 port c i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 list of figures mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor list of figures 25 figure title page 20-1 sim block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 20-2 sim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . 282 20-3 cgm clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 20-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20-6 sources of internal rese t. . . . . . . . . . . . . . . . . . . . . . . . . . 286 20-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 20-8 interrupt entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 20-9 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . 291 20-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 20-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . 293 20-12 interrupt status regist er 1 (int1) . . . . . . . . . . . . . . . . . . . 295 20-13 interrupt status regist er 2 (int2) . . . . . . . . . . . . . . . . . . . 295 20-14 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .297 20-15 wait recovery from interrupt or break. . . . . . . . . . . . . . . . 298 20-16 wait recovery from internal rese t . . . . . . . . . . . . . . . . . . 298 20-17 stop mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . .299 20-18 stop mode recovery fr om interrupt or break. . . . . . . . . . . 299 20-19 sim break status regi ster (sbsr) . . . . . . . . . . . . . . . . . . 300 20-20 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 301 20-21 sim break flag control register (sbfcr) . . . . . . . . . . . . 303 21-1 ssi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 21-2 transmission signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 21-3 ssi control register (s sicr) . . . . . . . . . . . . . . . . . . . . . . 313 21-4 ssi status register (s sisr) . . . . . . . . . . . . . . . . . . . . . . .315 21-5 ssi data register (ssi dr) . . . . . . . . . . . . . . . . . . . . . . . . 316 22-1 timebase block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 320 22-2 timebase control register (tbcr) . . . . . . . . . . . . . . . . . . 321 23-1 tim block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 23-2 tim i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . 328 23-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . 332 23-4 tim status and control register (t sc) . . . . . . . . . . . . . . . 338 23-5 tim counter register high (tcnth) . . . . . . . . . . . . . . . . . 340 list of figures advance information mc68hc908tv24 ? rev. 2.1 26 list of figures freescale semiconductor figure title page 23-6 tim counter register low (tcntl) . . . . . . . . . . . . . . . . . 340 23-7 tim counter modulo register high (tmodh) . . . . . . . . . . 341 23-8 tim counter modulo r egister low (tmodl). . . . . . . . . . . 341 23-9 tim channel 0 status and contro l register (tsc 0) . . . . . 342 23-10 tim channel 1 status and contro l register (tsc 1) . . . . . 342 23-11 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 23-12 tim channel 0 regist er high (tch0h) . . . . . . . . . . . . . . . 346 23-13 tim channel 0 regist er low (tch0l) . . . . . . . . . . . . . . . . 346 23-14 tim channel 1 regist er high (tch1h) . . . . . . . . . . . . . . . 347 23-15 tim channel 1 regist er low (tch1l) . . . . . . . . . . . . . . . . 347 24-1 mc68hc08tv24 block diagram . . . . . . . . . . . . . . . . . . . . 350 25-1 ssi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor list of tables 27 advance information ? mc68hc908tv24 list of tables table title page 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4-1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4-2 interrupt source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-1 numeric example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7-2 pre 1 and pre0 programming . . . . . . . . . . . . . . . . . . . . . . 116 7-3 vpr1 and vpr0 programming . . . . . . . . . . . . . . . . . . . . . . 116 8-1 line selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8-2 data slicer bias voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8-3 minimum vertical pulse width . . . . . . . . . . . . . . . . . . . . . . .139 11-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12-1 charge pump clock frequency . . . . . . . . . . . . . . . . . . . . . . 175 12-2 erase block sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13-1 charge pump clock frequency . . . . . . . . . . . . . . . . . . . . . . 189 13-2 erase block sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15-1 lviout bit indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16-1 mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17-1 shad1 and shad0 meaning. . . . . . . . . . . . . . . . . . . . . . . . 250 17-2 memory test mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 advance information mc68hc908tv24 ? rev. 2.1 28 list of tables freescale semiconductor list of tables table title page 18-1 port a pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 18-2 port b pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18-3 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 20-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 281 20-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 20-4 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 21-1 scl rates (hz) at bus frequency . . . . . . . . . . . . . . . . . . . .315 22-1 timebase rate selection for osc1 = 32.768 khz . . . . . . . . 321 23-1 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 23-2 mode, edge, and level se lection. . . . . . . . . . . . . . . . . . . . . 344 27-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 29 advance information ? mc68hc908tv24 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3.1 standard features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3.2 television applicati on specific features . . . . . . . . . . . . . . . 32 1.3.3 cpu08 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 36 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 37 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.5 cgm power supply pins (v ddcgm and v sscgm ) . . . . . . . . 37 1.6.6 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 37 1.6.7 power supply pin s for on-screen display (v ddosd and v ssosd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.8 external filter pins for on-screen display (osdvco and osdpmp). . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.9 synchronism signals (hsync and vsync) . . . . . . . . . . . . 38 1.6.10 color encoded pixel signals (r, g, b, and i). . . . . . . . . . . . 38 1.6.11 fast blanking signal (fbkg) . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.12 serial synchronous interfac e clocks (scl1 and scl2) . . . 38 1.6.13 serial synchronous interface data lines (sda1 and sda2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.6.14 video input (video ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.15 a/d converter input ( adcin) . . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.16 timer i/o pins (tch1 and tch0) . . . . . . . . . . . . . . . . . . . . 39 1.6.17 timer external clock input (tclk) . . . . . . . . . . . . . . . . . . . 39 1.6.18 port a i/o pins (pta7?p ta0) . . . . . . . . . . . . . . . . . . . . . . . 39 advance information mc68hc908tv24 ? rev. 2.1 30 general description freescale semiconductor general description 1.6.19 port b i/o pins (ptb7?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 39 1.6.20 port c i/o pins (ptc4?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 40 1.6.21 scan enable (scanen). . . . . . . . . . . . . . . . . . . . . . . . . . . .40 1.2 introduction the mc68hc908tv24 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontro ller units (mcus). all mcus in the family use the enhanced m68hc08 c entral processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. this part contains an embedded on- screen display module and a closed-caption controller, making it highly suitabl e for use as a low-cost tv or vcr mi crocontroller. 1.3 features for convenience, features of the mc68hc908tv24 have been organized to reflect: standard features television application-specific features cpu08 features 1.3.1 standard features high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families 8-mhz internal bus frequency 24 kbytes of on-chip flash memory 608 bytes of on-chip r andom-access memory (ram) 21 general-purpose input/output (i/o) pins general description features mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 31 flash program memory security 1 system protection features: ? optional computer operati ng properly (cop) reset ? low-voltage detection with optional reset and selectable trip points for 3.0-v and 5.0-v operation ? illegal opcode detection with reset ? illegal address detection with reset low-power design; fully st atic with stop and wait modes standard low-power modes of operation: ? wait mode ? stop mode 16-bit, 2-channel timer interfac e module (tim) with selectable input capture, output compar e, and pulse-width modulation (pwm) capability on each channel break module (brk) to allow single break point setting during in-circuit debugging clock generator module with on-c hip 32-khz crystal compatible pll (phase-lock loop) timebase module with clock presca ler circuitry for eight user selectable periodic real -time interrupts with ac tive clock source during stop mode for periodic wake up from stop using an external 32-khz crystal master reset pin and power-on reset (por) 52-pin plastic quad flat pack (pqfp) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficul t for unauthorized users. advance information mc68hc908tv24 ? rev. 2.1 32 general description freescale semiconductor general description 1.3.2 television application-specific features on-screen display (osd) controller ? works with either 525- or 625-line systems ? pixel matrix flash memory capable of storing 192 9 x 13 closed-caption characters and 128 12 x 18 on-screen display characters ? 16 rows by 34 columns in closed-caption mode ? 12 rows by 24 columns in on-screen display mode ? software selectable attribut es: 16 foreground and background colors, black outline, 3d-s hadow, underline, and italics ? two foreground colors are possibl e in one character by the use of backspace overlaying of two characters ? three on-screen display (osd) ch aracter sizes selectable on a row by row basis: (1 x 1), (1.5 x 2), and (2 x 2) ? programmable vertical and horizontal position ? software controlled features: soft scrolling and blinking ? support for video muting ? outputs: r, g, b, i, and fbkg, all with software programmable polarities closed-caption data slicer (dsl): ? fcc/eia-744 v-chip compatible ? fcc/eia-608 line 21 format data extraction on both field 1 and field 2 ? software programmable line selection (lines 14 to 29) ? hardware parity checking ? software programmable data slicing level serial synchronous interface (ssi) ? two independent data ports with single master i 2 c compatibility (both ports cannot be used simultaneously) analog-to-digital converte r (adc) ? 4-bits resolution general description mcu block diagram mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 33 1.3.3 cpu08 features features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908tv24. advance information mc68hc908tv24 ? rev. 2.1 34 general description freescale semiconductor general description figure 1-1. mc68h c908tv24 block diagram ptc system integration module on-screen display module break module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user flash memory ? 24,576 bytes user ram ? 608 bytes monitor rom ? 240 bytes user flash vector space ? 22 bytes single external irq module power pta ddra internal bus rst irq pta7?pta0 timer interface module data slicer module video 4-bit analog-to-digital converter module adcin tch1 tch0 tclk vsync hsync osdpmp scl1 sda1 sda2 v dd v ss v ddcgm v sscgm v ddosd v ssosd r, g, b, i, fbkg serial synchronous interface module scl2 osdvco clock generator module osc1 osc2 cgmxfc 32-khz oscillator phase-locked loop timebase module ptb ddrb ptb7?ptb0 ddrc ptc4?ptc0 osd flash memory ? 8,192 bytes configuration register security module general description pin assignments mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 35 1.5 pin assignments figure 1-2. pin assignments r v dd ptb6 scanen vsync hsync adcin video osdvco osdpmp g b i fbkg scl1 v sscgm v ddcgm cgmxfc osc1 osc2 irq ptb7 ptb5 ptb4 ptb3 ptb2 ptb1 tch0 tch1 tclk ptc1 ptc0 n/c v ssosd v ddosd rst ptc4 ptc3 ptc2 scl2 sda1 sda2 pta0 pta1 pta2 v ss pta3 pta4 pta5 pta6 pta7 ptb0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 advance information mc68hc908tv24 ? rev. 2.1 36 general description freescale semiconductor general description 1.6 pin functions descriptions of the pin f unctions are provided here. 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-3 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response cerami c capacitor for c1. c2 is an optional bulk current bypa ss capacitor for use in appl ications that require the port pins to sour ce high current levels. figure 1-3. power supply bypassing mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications. general description pin functions mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 37 1.6.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. see section 7. clock generator module (cgmc) . 1.6.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of t he entire system. it is driven low when any internal reset sour ce is asserted. see section 20. system integration module (sim) . 1.6.4 external interrupt pin (irq ) irq is an asynchronous exte rnal interrupt pin. see section 14. external interrupt (irq) . 1.6.5 cgm power supply pins (v ddcgm and v sscgm ) v ddcgm and v sscgm are the power supply pins for the analog portion of the clock generator modul e (cgm). decoupling of these pins should be as per the digital supply. see section 7. clock generator module (cgmc) . 1.6.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacito r connection for the cgm. see section 7. clock gene rator module (cgmc) . 1.6.7 power supply pins for on-screen display (v ddosd and v ssosd ) v ddosd and v ssosd are the power supply and ground pins for the analog part of the on-scree n display module (osd ). decoupling of these pins should be as per t he digital supply. see section 17. on-screen display module (osd) . advance information mc68hc908tv24 ? rev. 2.1 38 general description freescale semiconductor general description 1.6.8 external filter pins for on-screen display (osdvco and osdpmp) osdvco and osdpmp are two ex ternal filter pins used by the pll that extracts the osd clock from t he horizontal sync signal. see section 17. on-screen displ ay module (osd) . 1.6.9 synchronism signals (hsync and vsync) these are two input-only pins used by the on-screen display module to synchronize to the television signal. these pins contain internal schmitt triggers to improve noise immunity. see section 17. on-screen display module (osd) . 1.6.10 color encoded pixel signals (r, g, b, and i) these are the red, green, blue and intensity ou tput signals from the on-screen displa y module. see section 17. on -screen display module (osd) . 1.6.11 fast blanking signal (fbkg) fbkg is an output pin of the on-screen display module. it is used to blank the tv video when a pixel is being outputted on the r, g, b, and i pins. see section 17. on-scree n display module (osd) . 1.6.12 serial synchronous interface clocks (scl1 and scl2) scl1 and scl2 are open-drain i/o pins. they are the bidirectional clock lines of the serial synchr onous interface module. see section 21. serial synchronous interf ace module (ssi) . 1.6.13 serial synchronous interface data lines (sda1 and sda2) sda1 and sda2 are open-drai n i/o pins. they are t he bidirectional data lines of the serial synchr onous interface module. see section 21. serial synchronous interf ace module (ssi) . general description pin functions mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor general description 39 1.6.14 video input (video) this input-only analog pin is the com posite base-band video input signal for the data slicer module. see section 8. closed-c aption data slicer (dsl) . 1.6.15 a/d converter input (adcin) this is the analog input to the analog-to-digital converter module. see section 5. analog-to-d igital converter (adc4) . 1.6.16 timer i/o pins (tch1 and tch0) these pins are used by the time r interface modul e. they can be programmed independently as input capture or output compare pins. see section 23. timer in terface module (tim) . 1.6.17 timer external clock input (tclk) this is an external clock input for the time r module that can be used instead of the prescaled in ternal bus clock. see section 23. timer interface module (tim) . 1.6.18 port a i/o pins (pta7?pta0) pta7?pta0 are general- purpose, bidirectiona l i/o port pins. see section 18. input/output (i/o) ports . 1.6.19 port b i/o pins (ptb7?ptb0) ptb7?ptb0 are general- purpose, bidirectiona l i/o port pins. see section 18. input/output (i/o) ports . advance information mc68hc908tv24 ? rev. 2.1 40 general description freescale semiconductor general description 1.6.20 port c i/o pins (ptc4?ptc0) ptc4?ptc0 are general-purpose, bi directional i/o port pins. see section 18. input/output (i/o) ports . 1.6.21 scan enable (scanen) this pin is used only during production test and should be connected to v ss in all user applications. note: any unused inputs and i/o po rts should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908tv24 do not require te rmination, termination is recommended to reduce the possi bility of static damage. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 41 advance information ? mc68hc908tv24 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 24,064 bytes of user flash memory 8 kbytes of on-screen di splay (osd) flash memory 608 bytes of random-access memory (ram) 22 bytes of user-defined vectors 240 bytes of monitor r ead-only memory (rom) 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. advance information mc68hc908tv24 ? rev. 2.1 42 memory map freescale semiconductor memory map 2.4 reserved me mory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section addresses $0000?$004f, shown in figure 2-2 , contain most of the control, status, and data registers. additional input/output (i/o) registers have these addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe02; reserved, subar $fe03; sim break flag control register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; reserved, fl1tcr $fe07; user flash c ontrol register, fl1cr $fe08; reserved, fl2tcr $fe09; osd flash control register, fl2cr $fe0a; osd output con trol register, osdocr $fe0b; osd enable contro l register, osdectr $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; lvi status register, lvisr $ff80; user flash block protect register, fl1bpr $ff81; osd flash block protect register, fl2bpr $ffff; cop control register, copctl table 2-1 is a list of vector locations. memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 43 $0000 i/o registers 80 bytes $004f $0050 ram 608 bytes $02af $02b0 unimplemented 32,080 bytes $7fff $8000 osd flash memory 8,192 bytes $9fff $a000 user flash memory 24,064 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved (subar) $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 reserved (fl1tcr) $fe07 user flash control register (fl1cr) $fe08 reserved (fl2tcr) $fe09 osd flash control register (fl2cr) $fe0a osd output control register (osdocr) $fe0b osd enable contro l register (osdectr) $fe0c break address register high (brkh) $fe0d break address register low (brkl) figure 2-1. memory map advance information mc68hc908tv24 ? rev. 2.1 44 memory map freescale semiconductor memory map $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 monitor rom 240 bytes $feff $ff00 unimplemented 128 bytes $ff7f $ff80 user flash block protect register (fl1bpr) $ff81 osd flash block pr otect register (fl2bpr) $ff82 reserved 104 bytes $ffe9 $ffea flash vectors 22 bytes $ffff figure 2-1. memory map (continued) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 45 addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 269 . read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 272 . read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 274 . read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 unimplemented read: write: reset: unaffected by reset $0004 data direction register a (ddra) see page 270 . read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 273 . read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 275 . read: 0 0 0 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 irq status and control register (intscr) see page 199 . read: 0000irqf0 imask mode write: ack reset:00000000 $0008 pll control register (pctl) see page 114 . read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0009 pll bandwidth control register (pbwc) see page 117 . read: auto lock acq 0000 r write: reset:00000000 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 1 of 10) advance information mc68hc908tv24 ? rev. 2.1 46 memory map freescale semiconductor memory map $000a pll multiplier select high register (pmsh) see page 118 . read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $000b pll multiplier select low register (pmsl) see page 119 . read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $000c pll vco select range register (pmrs) see page 120 . read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $000d pll reference divider select register (pmds) see page 121 . read: 0000 rds3 rds2 rds1 rds0 write: reset:00000001 $000e configuration register ? (config) see page 144 . read: lvistop lvi5or3 ? lvirstd lvipwrd ssrec coprs stop copd write: reset:00000000 $000f timer status and control register (tsc) see page 337 . read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0010 timer counter register high (tcnth) see page 340 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0011 timer counter register low (tcntl) see page 340 . read: bit 7 654321bit 0 write: reset:00000000 $0012 timer counter modulo register high (tmodh) see page 341 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0013 timer counter modulo register low (tmodl) see page 341 . read: bit 7654321bit 0 write: reset:11111111 ? one-time writable register after each reset, except lvi5or3 bit. the lvi5or3 bit is only re set via por (power-on reset). addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 2 of 10) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 47 $0014 timer channel 0 status and control register (tsc0) see page 342 . read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0015 timer channel 0 register high (tch0h) see page 346 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0016 timer channel 0 register low (tch0l) see page 346 . read: bit 7654321bit 0 write: reset: indeterminate after reset $0017 timer channel 1 status and control register (tsc1) see page 342 . read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0018 timer channel 1 register high (tch1h) see page 346 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0019 timer channel 1 register low (tch1l) see page 346 . read: bit 7654321bit 0 write: reset: indeterminate after reset $001a timebase control register (tbcr) see page 321 . read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 $001b osd horizontal delay register (osdhdr) see page 252 . read: 0 0 0 hd4 hd3 hd2 hd1 hd0 write: reset:00000000 $001c osd foreground control register (osdfcr) see page 252 . read: chhs chws rnden boen fgi fgr fgb fgg write: reset:00000000 $001d osd background control register (osdbkcr) see page 254 . read: bkht shad1 shad0 bks bki bkr bkb bkg write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 3 of 10) advance information mc68hc908tv24 ? rev. 2.1 48 memory map freescale semiconductor memory map $001e osd matrix start register (osdmsr) see page 263 . read: dmode blink 0 ms4 ms3 ms2 ms1 ms0 write: reset:00000000 $001f osd matrix end register (osdmer) see page 265 . read: 0 0 0 me4 me3 me2 me1 me0 write: reset:00000000 $0020 osd character 1 (osdchar1) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0021 osd character 2 (osdchar2) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0022 osd character 3 (osdchar3) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0023 osd character 4 (osdchar4) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0024 osd character 5 (osdchar5) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0025 osd character 6 (osdchar6) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0026 osd character 7 (osdchar7) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0027 osd character 8 (osdchar8) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 4 of 10) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 49 $0028 osd character 9 (osdchar9) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0029 osd character 10 (osdchar10) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002a osd character 11 (osdchar11) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002b osd character 12 (osdchar12) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002c osd character 13 (osdchar13) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002d osd character 14 (osdchar14) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002e osd character 15 (osdchar15) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $002f osd character 16 (osdchar16) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0030 osd character 17 (osdchar17) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0031 osd character 18 (osdchar18) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 5 of 10) advance information mc68hc908tv24 ? rev. 2.1 50 memory map freescale semiconductor memory map $0032 osd character 19 (osdchar19) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0033 osd character 20 (osdchar20) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0034 osd character 21 (osdchar21) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0035 osd character 22 (osdchar22) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0036 osd character 23 (osdchar23) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0037 osd character 24 (osdchar24) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0038 osd character 25 (osdchar25) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0039 osd character 26 (osdchar26) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $003a osd character 27 (osdchar27) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $003b osd character 28 (osdchar28) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 6 of 10) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 51 $003c osd character 29 (osdchar29) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $003d osd character 30 (osdchar30) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $003e osd character 31 (osdchar31) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $003f osd character 32 (osdchar32) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0040 osd character 33 (osdchar33) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0041 osd character 34 (osdchar34) see page 245 . read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset $0042 osd vertical delay register (osdvdr) see page 251 . read: 0 0 vd5 vd4 vd3 vd2 vd1 vd0 write: reset:00000000 $0043 osd border control register (osdbcr) see page 255 . read: blinken boht vmute bos boi bor bob bog write: reset:00000000 $0044 osd event line register (osdelr) see page 259 . read: el7el6el5el4el3el2el1el0 write: reset:00000000 $0045 osd event count register (osdecr) see page 260 . read: ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 7 of 10) advance information mc68hc908tv24 ? rev. 2.1 52 memory map freescale semiconductor memory map $0046 osd status register (osdsr) see page 262 . read: elmf vsinf hsyn vsyn 0 vcotst dsltst plltst write: reset:10xx0000 $0047 dsl character register 1 (dslch1) see page 135 . read: pe da6 da5 da4 da3 da2 da1 da0 write: reset:0xxxxxxx $0048 dsl character register 2 (dslch2) see page 135 . read: pe da6 da5 da4 da3 da2 da1 da0 write: reset:0xxxxxxx $0049 dsl control register 1 (dslcr1) see page 136 . read: dsien dsen vven line4 line3 line2 line1 disclp write: reset:00000000 $004a dsl control register 2 (dslcr2) see page 138 . read: vr1 vr0 pw1 pw0 vpd syncmp datcmp blkcmp write: reset:00000000 $004b dsl status register (dslsr) see page 141 . read: dsfl ovfl field1 0 csync vpdet ric1 ric0 write: reset:0000x000 $004c ssi control register (ssicr) see page 313 . read: sie se start stop ack schs sr1 sr0 write: reset:00000000 $004d ssi status register (ssisr) see page 315 . read: sf dcol 000000 write: reset:00000000 $004e ssi data register (ssidr) see page 316 . read: da7 da6 da5 da4 da3 da2 da1 da0 write: reset:00000000 $004f adc control and status register (adccsr) see page 84 . read: result adon 00 ad3 ad2 ad1 ad0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 8 of 10) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 53 $fe00 sim break status register (sbsr) see page 300 . read: 000100bw0 write:rrrrrrnoter reset:00010000 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) see page 301 . read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe02 sim upper byte address register (subar) read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) see page 303 . read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 199 . read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 199 . read: 00000if9if8if7 write:rrrrrrrr reset:00000000 $fe06 user flash test control register (fl1tcr) read: rrrrrrrr write: reset:00000000 $fe07 user flash control register (fl1cr) see page 173 . read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 $fe08 osd flash test control register (fl2tcr) read: rrrrrrrr write: reset:00000000 $fe09 osd flash control register (fl2cr) see page 187 . read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, st atus, and data regist ers (sheet 9 of 10) advance information mc68hc908tv24 ? rev. 2.1 54 memory map freescale semiconductor memory map $fe0a osd output control register (osdocr) see page 260 . read: 0 hinv vinv fdinv cinv fbinv iinv 0 write: reset:00000000 $fe0b osd enable control register (osdectr) see page 257 . read: osden elien vsien xfer pllen mem1 mem0 scan write: reset:00000000 $fe0c break address register high (brkh) see page 93 . read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) see page 93 . read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) see page 92 . read: brke brka 000000 write: reset:00000000 $fe0f lvi status register (lvisr) see page 205 . read: lviout 0000000 write: reset:00000000 $ff80 user flash block protect register (fl1bpr) ? see page 182 . read: rrrrbpr3bpr2bpr1bpr0 write: reset:uuuuuuuu $ff81 osd flash block protect register (fl2bpr) ? see page 193 . read: rrrrbpr3bpr2bpr1bpr0 write: reset:uuuuuuuu $ffff cop control register (copctl) see page 150 . read: low byte of reset vector write: writing clears cop counter, any value reset: unaffected by reset ? non-volatile flash register addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected x = indeterminate figure 2-2. control, status, and da ta registers (s heet 10 of 10) memory map input/output (i/o) section mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor memory map 55 table 2-1. vector addresses vector priority vector address vector lowest if9 $ffea ssi vector (high) $ffeb ssi vector (low) if8 $ffec dsl vector (high) $ffed dsl vector (low) if7 $ffee osd vector (high) $ffef osd vector (low) if6 $fff0 tim overflow vector (high) $fff1 tim overflow vector (low) if5 $fff2 tim channel 1 vector (high) $fff3 tim channel 1 vector (low) if4 $fff4 tim channel 0 vector (high) $fff5 tim channel 0 vector (low) if3 $fff6 timebase vector (high) $fff7 timebase vector (low) if2 $fff8 pll vector (high) $fff9 pll vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) advance information mc68hc908tv24 ? rev. 2.1 56 memory map freescale semiconductor memory map mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-power modes 57 advance information ? mc68hc908tv24 section 3. low-power modes 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.3 a/d converter (adc4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.4 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.5 central processor unit ( cpu). . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.6 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.7 closed-caption data slicer module ( dsl) . . . . . . . . . . . . . . . . 61 3.8 computer operating prop erly module (cop). . . . . . . . . . . . . . 61 3.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.9 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . .61 3.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.10 low-voltage inhibit module (lvi) . . . . . . . . . . . . . . . . . . . . . . . 62 3.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.11 on-screen display module (osd) . . . . . . . . . . . . . . . . . . . . . . 62 3.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.12 serial synchronous interface module (ssi) . . . . . . . . . . . . . . . 63 advance information mc68hc908tv24 ? rev. 2.1 58 low-power modes freescale semiconductor low-power modes 3.13 timer interface module (t im) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.14 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.14.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.14.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.15 exiting wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.16 exiting stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.2 introduction the mcu may enter two low-power modes: wait mode and stop mode. they are common to all hc08 mcus and are entered through instruction execution. this section describes how each module acts in the low-power modes. 3.2.1 wait mode the wait instruction puts the mcu in a low-power standby mode in which the cpu clock is disabled but the bus cl ock continues to run. power consumption can be further r educed by disabli ng the low-voltage inhibit (lvi) module through bits in the configuration (c onfig) register. (see section 9. configura tion register (config) .) 3.2.2 stop mode stop mode is entered w hen a stop instruction is executed. the cpu clock and the bus clock ar e disabled but the osci llator itself does not stop, continuing to feed clo ck to the timebase module. low-power modes a/d converter (adc4) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-power modes 59 3.3 a/d converter (adc4) the analog-to-digital (a/d) converter module will no t work in wait and stop modes. to achieve low-power c onsumption, it is recommended that the adc4 module be di sabled before entering wait or stop modes. 3.4 break module (brk) 3.4.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if the bw bit in the break stat us register is set. 3.4.2 stop mode the break module is inactive in stop mode. a break interrupt causes exit from stop mode and sets the bw bit in the br eak status register. the stop instruction does not affect break modu le register states. 3.5 central processor unit (cpu) 3.5.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock advance information mc68hc908tv24 ? rev. 2.1 60 low-power modes freescale semiconductor low-power modes 3.5.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 3.6 clock generator module (cgm) 3.6.1 wait mode the cgm remains active in wait m ode. before entering wait mode, software can disengage and turn of f the phase-locked loop (pll) by clearing the bcs an d pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applicat ions that require the p ll to wake the mcu from wait mode also can dese lect the pll output with out turning off the pll. 3.6.2 stop mode the stop instruction disables the p ll but the oscillato r will continue to operate. if the stop instruction is execut ed with the vco clock, cgmvclk, divided by two driving cg mout, the pll automatic ally clears the bcs bit in the pll control regi ster (pctl), thereby sele cting the crystal clock, cgmxclk, divided by two as the so urce of cgmout . when the mcu recovers from stop, th e crystal clock divided by two drives cgmout and bcs remains clear. low-power modes closed-caption data slicer module (dsl) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-power modes 61 3.7 closed-caption data slicer module (dsl) the dsl remains active during wait mode and stop mode; however, it will be unable to interrup t the cpu and bring it out of these modes. it is recommended that the dsl be disabled during wait mode or stop mode. 3.8 computer operating properly module (cop) 3.8.1 wait mode the cop remains active in wait mo de. to prevent a cop reset during wait mode, periodically cl ear the cop counter in a cpu interrupt routine. 3.8.2 stop mode stop mode turns off the cgmxclk i nput to the cop a nd clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. the stop bit in the config register enables the stop instruction. to prevent inadvertently tu rning off the cop with a stop instruction, disable the stop instructi on by clearing the stop bit. 3.9 external interrupt module (irq) 3.9.1 wait mode the irq module remains acti ve in wait mode. cl earing the imask1 bit in the irq status and control register (intscr) enables irq cpu interrupt requests to brin g the mcu out of wait mode. advance information mc68hc908tv24 ? rev. 2.1 62 low-power modes freescale semiconductor low-power modes 3.9.2 stop mode the irq module remains active in st op mode. clearing the imask1 bit in the irq status and control register (intscr) enables irq cpu interrupt requests to bring the mcu out of stop mode. 3.10 low-voltage inhibit module (lvi) 3.10.1 wait mode if enabled, the lvi module remains acti ve in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 3.10.2 stop mode if enabled, the lvi module remains acti ve in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. 3.11 on-screen display module (osd) 3.11.1 wait mode the osd remains active during wait mode, but it will be unable to interrupt the cpu and bring it out of this mode. it is recommended that the osd and pll be disabled before entering wait mode, unless a single row of fixed video output is desired to be displayed constantly. 3.11.2 stop mode although the osd module and the pll are no t automatically disabled in stop mode, the flash me mory will be disabled. as a consequence, the osd module will not work. it is recommended that the osd and pll be disabled before entering stop mode. low-power modes serial synchronous interface module (ssi) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-power modes 63 3.12 serial synchronou s interface module (ssi) in wait mode or stop m ode, the ssi halts operat ion. pins sda1, scl1, sda2, and scl2 will main tain their states. if the ssi is nearing completion of a transfer when wait mode or stop mode is entered, it is possible for the ssi to generate an interrupt request and thus cause t he processor to exit wait mode or stop mode immediately. to prevent this occurr ence, the programmer should ensure that all transfers are co mplete before entering wa it mode or stop mode. 3.13 timer interface module (tim) 3.13.1 wait mode the tim remains active in wait mode. any enabled cpu interrupt request from the tim can bri ng the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 3.13.2 stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or t he state of the tim count er. tim operation resumes when the mcu exits stop mode after an external interrupt. 3.14 timebase module (tbm) 3.14.1 wait mode the timebase module remains active after execution of the wait instruction. in wait m ode, the timebase r egister is not accessible by the cpu. advance information mc68hc908tv24 ? rev. 2.1 64 low-power modes freescale semiconductor low-power modes if the timebase functions are not r equired during wait mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 3.14.2 stop mode the timebase module remains active after execution of the stop instruction. the timebas e module can be used in this mode to generate a periodic wakeup from stop mode. in stop mode, the timebase register is not accessible by the cpu. if the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the stop instruction. 3.15 exiting wait mode these events restart the cpu clock a nd load the program counter with the reset vector or with an interrupt vector: external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of $fffe and $ffff. external interrupt ? a high-to- low transition on the external interrupt pin (irq ) loads the program count er with the contents of $fffa and $fffb. break interrupt ? a break inte rrupt loads the program counter with the contents of $fffc and $fffd. computer operating properly module (cop) reset ? a timeout of the cop counter resets the mcu and loads the program counter with the contents of $fffe and $ffff. low-voltage inhibit module (lvi) reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with t he contents of $fffe and $ffff. clock generator module (cgm) interrupt ? a cpu interrupt request from the phase-locked loop (pll) loads the program counter with t he contents of $fff8 and $fff9. low-power modes exiting stop mode mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-power modes 65 timer interface module (tim) in terrupt ? a cpu interrupt request from the tim loads th e program counter wi th the contents of: ? $fff0 and $fff1; tim1 overflow ? $fff2 and $fff3; tim1 channel 1 ? $fff4 and $fff5; tim1 channel 0 timebase module (tbm) interrupt ? a cpu interrupt request from the tbm loads the pr ogram counter with the contents of $fff6 and $fff7. 3.16 exiting stop mode these events restart the system clo cks and load the pr ogram counter with the reset vector or with an interrupt vector: external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of $fffe and $ffff. external interrupt ? a high-to-low transition on irq pin loads the program counter with the contents of $fffa and $fffb. low-voltage inhibit (lvi) reset ? a power supply voltage below the lvi tripf voltage resets the mc u and loads the program counter with t he contents of $fffe and $ffff. break interrupt ? a break inte rrupt loads the program counter with the contents of $fffc and $fffd. timebase module (tbm) interrupt ? a tbm interrupt loads the program counter with the cont ents of $fff6 and $fff7 when the timebase counter has ro lled over. this allows the tbm to generate a periodic wakeup from stop mode. upon exit from stop mode, the system clo cks begin running after an oscillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks for 4096 cg mxclk cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the configuration register controls the oscillator stabilizati on delay during stop recovery. setting advance information mc68hc908tv24 ? rev. 2.1 66 low-power modes freescale semiconductor low-power modes ssrec reduces stop recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. note: use the full stop recovery time (ss rec = 0) in applicat ions that use an external crystal. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 67 advance information ? mc68hc908tv24 section 4. resets and interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.3 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.3.2 computer operati ng properly (cop) reset. . . . . . . . . . . 70 4.3.3.3 low-voltage inhibit (l vi) reset . . . . . . . . . . . . . . . . . . . . 70 4.3.3.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.3.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.3.4 system integrati on module (sim) reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.2 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.2.1 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.2.2 break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.2.3 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.4.2.4 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . 77 4.4.2.5 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.2.6 timer (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.2.7 on-screen display (osd ) . . . . . . . . . . . . . . . . . . . . . . . .78 4.4.2.8 data slicer (dsl) modul e . . . . . . . . . . . . . . . . . . . . . . . .78 4.4.2.9 serial synchronous interface ( ssi) module . . . . . . . . . . . 78 4.4.3 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.3.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4.3.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . . 80 advance information mc68hc908tv24 ? rev. 2.1 68 resets and interrupts freescale semiconductor resets and interrupts 4.2 introduction resets and interrupts are responses to exceptional events during program execution. a reset re-initializ es the mcu to its startup condition. an interrupt vectors the program counter to a service routine. 4.3 resets a reset immediately retu rns the mcu to a know n startup condition and begins program execution from a user-defined memory location. 4.3.1 effects a reset: immediately stops the operation of the instruction being executed initializes certain c ontrol and status bits loads the program counter with a user-defined reset vector address from locations $fffe and $ffff selects cgmxclk divided by four as the bus clock 4.3.2 external reset a logic 0 applie d to the rst pin for a time, t irl , generates an external reset. an external reset sets the pi n bit in the system integration module (sim) reset status register. 4.3.3 internal reset sources: power-on reset (por) computer operating properly (cop) low-voltage inhibit (lvi) illegal opcode illegal address resets and interrupts resets mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 69 all internal reset sources pull the rst pin low for 32 cgmxclk cycles to allow resetting of external devices. the mcu is held in reset for an additional 32 cgmxclk cycles after releasing the rst pin. figure 4-1. inter nal reset timing 4.3.3.1 power-on reset (por) a power-on reset (por) is an inte rnal reset caused by a positive transition on the v dd pin. v dd at the por must go completely to 0 v to reset the mcu. this di stinguishes between a re set and a por. the por is not a brown-out dete ctor, low-voltage detector, or glitch detector. a power-on reset: holds the clocks to the cpu and modul es inactive for an oscillator stabilization delay of 4096 cgmxclk cycles drives the rst pin low during the osci llator stabilization delay releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay releases the cpu to begin the reset vector sequence 64 cgmxclk cycles after the o scillator stabilization delay sets the por and lp bits in t he sim reset status register and clears all other bi ts in the register rst pin pulled low by mcu internal 32 cycles 32 cycles cgmxclk reset advance information mc68hc908tv24 ? rev. 2.1 70 resets and interrupts freescale semiconductor resets and interrupts figure 4-2. power- on reset recovery 4.3.3.2 computer operat ing properly (cop) reset a cop reset is an internal reset caused by an overflow of the cop counter. a cop reset sets the cop bi t in the system integration module (sim) reset status register. to clear the cop counter and prevent a cop rese t, write any value to the cop control register at location $ffff. 4.3.3.3 low-voltage inhibit (lvi) reset an lvi reset is an internal reset c aused by a drop in the power supply voltage to the lvi tripf voltage. an lvi reset: holds the clocks to the cpu and modul es inactive for an oscillator stabilization delay of 4096 cgmx clk cycles after the power supply voltage rises to the lvi tripr voltage drives the rst pin low for as long as v dd is below the lvi tripr voltage and during the oscill ator stabilization delay releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay porrst (1) osc1 cgmxclk cgmout rst pin internal 4096 cycles 32 cycles 32 cycles 1. porrst is an internally generated power-on reset pulse. reset resets and interrupts resets mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 71 releases the cpu to begin the reset vector sequence 64 cgmxclk cycles after the o scillator stabilization delay sets the lvi bit in the sim reset status register 4.3.3.4 illegal opcode reset an illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. an illegal opcode reset sets the ilop bit in the sim reset status register. if the stop enable bit, st op, in the mask option regi ster (mor) is a logic 0, the stop instruction c auses an illegal opcode reset. 4.3.3.5 illegal address reset an illegal address reset is an internal reset caused by opcode fetch from an unmapped address. an illegal address re set sets the ilad bit in the sim reset status register. a data fetch from an unmapped addr ess does not generate a reset. 4.3.4 system integration module (sim) reset status register the sim reset status regi ster (srsr) is a read- only register containing flags to show reset sources. all flag bits are automatically cleared following a read of the register. re set service can re ad the sim reset status register to clear the regist er after power-on reset and to determine the source of any subsequent reset. the register is initialized on power- up as shown with the por bit set and all other bits cleared. during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 xclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the srsr may be set in addition to whatever other bits are set. advance information mc68hc908tv24 ? rev. 2.1 72 resets and interrupts freescale semiconductor resets and interrupts note: only a read of the sim reset status r egister clears all re set flags. after multiple resets from different sources without reading the register, multiple flags remain set. por ? power-on reset flag bit 1 = power-on reset sinc e last read of srsr 0 = read of srsr sinc e last power-on reset pin ? external reset flag bit 1 = external reset via rst pin since last read of srsr 0 = por or read of srsr si nce last external reset cop ? computer operati ng properly reset bit 1 = last reset caused by timeout of cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset caused by low-power supply voltage 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented figure 4-3. sim reset status register (srsr) resets and interrupts interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 73 4.4 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a particular event. an inte rrupt does not stop the operation of the instruction being executed, but begins when the curr ent instruction completes its operation. 4.4.1 effects an interrupt: saves the cpu registers on the stac k. at the end of the interrupt, the rti instruction recovers the cpu registers from the stack so that normal processi ng can resume. (see figure 4-4 .) sets the interrupt mask (i bit) to prevent additi onal interrupts. once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. loads the program counter with a user-defined vector address after every instruction, the cpu c hecks all pending interrupts if the i bit is not set. if more th an one interrupt is pendi ng when an instruction is done, the highest priority interrupt is serviced first. in the example shown in figure 4-5 , if an interrupt is pending upon exit from the interrupt service routine, the pending interr upt is serviced before the load accumulator (lda) instruction is executed. the lda opcode is prefetch ed by both the int1 and int2 return-from-interrupt (rti) instructions . however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed add ressing mode, save the h register and then restore it prior to exiti ng the routine. advance information mc68hc908tv24 ? rev. 2.1 74 resets and interrupts freescale semiconductor resets and interrupts figure 4-4. interr upt stacking order figure 4-5 . interrupt recogni tion example condition code register accumulator index register (low byte)* program counter (high byte) program counter (low byte) 1 2 3 4 5 5 4 3 2 1 stacking order *high byte of index register is not stacked. $00ff default address on reset unstacking order cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine resets and interrupts interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 75 figure 4-6. interrupt processing no no no yes no no yes no yes yes from reset break i bit set? irq interrupt cgm interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? interrupt yes other interrupts no swi instruction rti instruction ? ? ? ? ? ? advance information mc68hc908tv24 ? rev. 2.1 76 resets and interrupts freescale semiconductor resets and interrupts 4.4.2 sources the sources in table 4-1 can generate cpu interrupt requests. 4.4.2.1 swi instruction the software interrupt instruct ion (swi) causes a non-maskable interrupt. note: a software interrupt pushes pc onto the stack. an swi does not push pc ? 1, as a hardware interrupt does. 4.4.2.2 break interrupt the break module causes the cpu to execute an swi instruction at a software-programmable break point. table 4-1. interrupt sources source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag priority (2) 2. 0 = highest priority vector address reset none none none 0 $fffe ? $ffff swi instruction none none none 0 $fffc ? $fffd irq pin irqf imask1 if1 1 $fffa ? $fffb cgm (pll) pllf pllie if2 2 $fff8?$fff9 timebase tbif tbie if3 3 $fff6?$fff7 tim channel 0 ch0f ch0ie if4 4 $fff4?$fff5 tim channel 1 ch1f ch1ie if5 5 $fff2?$fff3 tim overflow tof toie if6 6 $fff0?$fff1 osd event line match elmf elien if7 7 $ffee?$ffef osd vertical sync pulse vsinf vsien closed-caption data slicer dsfl dsien if8 8 $ffec?$ffed serial synchronous interface sf sie if9 9 $ffea?$ffeb notes: resets and interrupts interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 77 4.4.2.3 irq pin a logic 0 on the irq pin latches an exter nal interrupt request. 4.4.2.4 clock gener ator module (cgm) the clock generator module (cgm) can generate a cpu interrupt request every time th e phase-locked loop circuit (pll) enters or leaves the locked state. when the lock bit changes stat e, the pll flag (pllf) is set. the pll interrupt enable bit (pllie) enabl es pllf cpu interrupt requests. lock is in the pll bandwidth control re gister. pllf is in the pll control register. 4.4.2.5 timebase module (tbm) the timebase module (tbm) can inte rrupt the cpu on a regular basis with a rate defined by tbr2?tbr0. when the ti mebase counter chain rolls over, the tbif flag is set. if the tbie bi t is set, enabling the timebase interrupt, the counter chain overflow will gene rate a cpu interrupt request. interrupts must be acknowledged by writing a logic 1 to the tack bit. 4.4.2.6 timer (tim) timer (tim) cpu interrupt sources: tim overflow flag (tof) ? th e tof bit is set when the tim counter value rolls over to $0000 after matching t he value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim stat us and control register. tim channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxi e, enables channel x tim cpu interrupt requests. chxf and chx ie are in the tim channel x status and control register. advance information mc68hc908tv24 ? rev. 2.1 78 resets and interrupts freescale semiconductor resets and interrupts 4.4.2.7 on-screen display (osd) on-screen display (osd) cpu interrupt sources: event line match flag (elmf) ? th is flag is located on the osd status register (osdsr ). it is set when t he osd scan line counter matches the value pr ogrammed on the ev ent line register (osdelr). this flag generates an inte rrupt if the elien bit of the osd enable control regist er (osdectr) is set. vertical sync flag (vsinf) ? thi s flag is located on the osd status register (osdsr). it is se t at every starting edge of vsync pulses. this flag generates an interr upt if the vsien bit of the osd enable control register (osdectr) is set. interrupts must be ackn owledged by writing any va lue to the osd status register (osdsr). 4.4.2.8 data s licer (dsl) module the data slicer (dsl) module can interrupt the cpu to indica te that it has sampled 16 bits of clos ed-caption data (including parity) and has placed them in registers ds lch1 and dslch2. when this happens, the dsfl bit of the dsl status register (d slsr) is asserted and an interrupt is issued if the dsien bit on the dsl control regist er 1 (dslcr1) is set. interrupts must be acknowledged by wr iting any value to the dsl status register (osdsr). 4.4.2.9 serial synchronou s interface (ssi) module the serial synchronous interface (ssi ) module can interr upt the cpu to indicate that one complete transfe r has occurred. when this happens, the sf bit of the ssi status register (ssisr) is asserted and an interrupt is issued if the sie bit of the ss i control register (ssicr) is set. resets and interrupts interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor resets and interrupts 79 the sf flag must always be cleared between transfers . this can be done in three ways: 1. by reading the ssi status register with sf set, followed by writing or reading the ssi dat a register (ssidr) 2. by a reset 3. by disabling the ssi note: if the sf flag is cleared by resetti ng or disabling the ssi before issuing a stop bit, the slave device may enter into an indeterminate state. the first method of clearing sf is always the best. 4.4.3 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 4-2 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 4-2. interrupt source flags interrupt source interrupt status register flag reset ? swi instruction ? irq pin if1 cgm (pll) if2 timebase if3 tim channel 0 if4 tim channel 1 if5 tim overflow if6 on-screen display if7 closed-caption data slicer if8 serial synchronous interface if9 advance information mc68hc908tv24 ? rev. 2.1 80 resets and interrupts freescale semiconductor resets and interrupts 4.4.3.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 4-2 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 4.4.3.2 interrupt status regist er 2 if9?if7 ? interrupt flags 9?7 these flags indicate the presence of interrupt r equests from the sources shown in table 4-2 . 1 = interrupt request present 0 = no interrupt request present bits 7?3 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 4-7. interrupt status register 1 (int1) address: $fe05 bit 7654321bit 0 read: 00000if9if8if7 write:rrrrrrrr reset:00000000 r= reserved figure 4-8. interrupt status register 2 (int2) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor analog-to-digital converter (adc4) 81 advance information ? mc68hc908tv24 section 5. analog-to-digital converter (adc4) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.5.2 conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.5.3 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6 adc control and status register . . . . . . . . . . . . . . . . . . . . . . . 84 5.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 introduction the analog-to-digital converter ( adc4) performs individual analog comparisons that can be used together with a software algorithm to obtain an analog-to-digital conversion. 5.3 feature the adc4 provides t he following feature: 4-bit software analog- to-digital conversion advance information mc68hc908tv24 ? rev. 2.1 82 analog-to-digital converter (adc4) freescale semiconductor analog-to-digital converter (adc4) 5.4 overview the adc4 system consists of a si ngle 4-bit analog-to-digital (a/d) converter and comparator with cont inuous conversion. a result flag indicates if the compar ator output is above or below the an alog input, adcin. (see figure 5-1 .) figure 5-1. adc 4 block diagram 5.5 programming guidelines the following subsections descr ibe programming guidelines. 5.5.1 setup the adc4 must be enabled by setting the adon bit in the adc control and status register (adccsr). ? + register adccsr r2r reference decode result adval enable data addr/control hc08 internal bus a/d converter adcin analog-to-digital converter (adc4) programming guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor analog-to-digital converter (adc4) 83 5.5.2 conversions an a/d conversion can be perform ed with the aid of a software algorithm. figure 5-2 shows an example of a conversion code. figure 5-2. adc co nversion code example 5.5.3 input/output the adc4 has one input pi n (adcin), which is t he analog input to be converted. lda# #$40 ; enable adc sta adccsr ; and set initial a/d value = 00 inc atd ; no real function other than dec atd ; having the required initial delay dta: sta atd ; save a/d value lda adccsr and #$8f ; read comparator result and a/d value cmp #$0f ; check if reached analog pin ; value or a/d value is maximum bge endc ; if ok, end of conversion inc adccsr ; if not, increment a/d value bra dta ; return endc: ... atd ... ; analog value in adc ; analogin=(adc+1)*0.3125v with v dd =5v advance information mc68hc908tv24 ? rev. 2.1 84 analog-to-digital converter (adc4) freescale semiconductor analog-to-digital converter (adc4) 5.6 adc control and status register the adc control and status register ( adccsr) contains al l of the adc4 status and control bits. result ? comparat or result bit this bit indicates the relationship of the analog input to the analog version of the ad3?ad0 value. a reset has no effe ct on this bit. 1 = d/a output analog in 0 = d/a output < analog in adon ? adc on bit this bit indicates wh ether the adc is enabl ed. when enabled, the adc supplies power to the d/a resist ive ladder. a reset clears this bit. 1 = adc enabled 0 = adc disabled note: if not in use, the in put should be tied to v ss and a value of $00 should be written to the adc cont rol and status register. ad3:ad0 ? adc comparison value bits these bits are controlled by th e user to perform a successive approximation conversion in softwa re. when a value causes the result bit to change st ate from the value im mediately before or after it, ad3:ad0 are considered to be the digital eq uivalent of the analog input. a reset clears these bits. address: $004f bit 7654321bit 0 read: result adon 00 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 5-3. adc control and status register (adccsr) analog-to-digital converter (adc4) low-power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor analog-to-digital converter (adc4) 85 5.7 low-power modes the adc4 will not work in wait mode and stop m ode. to achieve low-power consumption, it is reco mmended that the adc 4 be disabled before entering wait mode or stop mode. 5.8 interrupts and resets the adc4 does not interrupt or reset the cpu. advance information mc68hc908tv24 ? rev. 2.1 86 analog-to-digital converter (adc4) freescale semiconductor analog-to-digital converter (adc4) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor break module (brk) 87 advance information ? mc68hc908tv24 section 6. break module (brk) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . . 90 6.4.2 cpu during break interr upts . . . . . . . . . . . . . . . . . . . . . . . .90 6.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.4 cop during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.6.1 break status and control register. . . . . . . . . . . . . . . . . . . . 92 6.6.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.6.3 sim break status regist er . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . . 95 6.2 introduction this section describes the break module (brk). the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. advance information mc68hc908tv24 ? rev. 2.1 88 break module (brk) freescale semiconductor break module (brk) 6.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 6.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the progr am counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 6-1 shows the structure of the break module. break module (brk) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor break module (brk) 89 figure 6-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 94. read: 000100bw0 write:rrrrrrnoter reset:00010000 $fe03 sim break flag control register (sbfcr) see page 95. read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) see page 93. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) see page 93. read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) see page 92. read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears bw. = unimplemented r = reserved figure 6-2. i/o register summary advance information mc68hc908tv24 ? rev. 2.1 90 break module (brk) freescale semiconductor break module (brk) 6.4.1 flag protection during break interrupts the bcfe bit in the system integrati on module (sim) brea k flag control register (sbfcr) enables software to clear status bits during the break state. 6.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 6.4.3 tim during break interrupts a break interrupt stops the timer counters. 6.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 6.5 low-power modes the wait and stop instruct ions put the mcu in low power-consumption standby modes. break module (brk) break module registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor break module (brk) 91 6.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set. see section 3. low-power modes . clear the bw bit by writing logic 0 to it. 6.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 6.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag con trol register (sbfcr) advance information mc68hc908tv24 ? rev. 2.1 92 break module (brk) freescale semiconductor break module (brk) 6.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a br eak interrupt. clear brka by writing a l ogic 0 to it before exit ing the break routine. reset clears the brka bit. 1 = when read, brea k address match 0 = when read, no br eak address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 6-3. break status and control register (brkscr) break module (brk) break module registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor break module (brk) 93 6.6.2 break address registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 6-4. break addr ess register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 6-5. break address register low (brkl) advance information mc68hc908tv24 ? rev. 2.1 94 break module (brk) freescale semiconductor break module (brk) 6.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. bw ? break wait bit this read/write bit is se t when a break interrupt causes an exit from wait mode. clear bw by writing a logic 0 to it. reset clears bw. 1 = break interrupt during wait mode 0 = no break interr upt during wait mode bw can be read within the break interr upt routine. the user can modify the return address on the stack by s ubtracting 1 from it. the example code shown in figure 6-7 works if the h regist er was stacked in the break interrupt routine. execute this code at the end of the break interrupt routine. figure 6-7. example code address: $fe00 bit 7654321bit 0 read: 000100bw0 write:rrrrrrnoter reset:00010000 note: writing a logic 0 clears bw. r = reserved figure 6-6. sim break status register (sbsr) hibyte equ 5 lobyte equ 6 ; if not bw, do rti brclr bw,bsr, return ; see if wait mode or stop ; mode was exited by break. tst lobyte,sp ; if returnlo is not 0, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte also. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. break module (brk) break module registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor break module (brk) 95 6.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 6-8. sim break flag control register (sbfcr) advance information mc68hc908tv24 ? rev. 2.1 96 break module (brk) freescale semiconductor break module (brk) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 97 advance information ? mc68hc908tv24 section 7. clock generator module (cgmc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . 101 7.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . 102 7.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . 103 7.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.4.7 special programming exceptions . . . . . . . . . . . . . . . . . . . 108 7.4.8 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4.9 cgmc external connections . . . . . . . . . . . . . . . . . . . . . . . 109 7.5 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 110 7.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 110 7.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 111 7.5.4 pll analog power pin (v ddcgm ). . . . . . . . . . . . . . . . . . . .111 7.5.5 pll anal og ground pin (v sscgm ) . . . . . . . . . . . . . . . . . . . 111 7.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 111 7.5.7 cgmc base clock output (cgmou t) . . . . . . . . . . . . . . . 112 7.5.8 cgmc cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . 112 7.6 cgmc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.6.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . .117 7.6.3 pll multiplier select register high . . . . . . . . . . . . . . . . . . 118 7.6.4 pll multiplier select register low. . . . . . . . . . . . . . . . . . . 119 7.6.5 pll vco range select register . . . . . . . . . . . . . . . . . . . .120 7.6.6 pll reference divider select register . . . . . . . . . . . . . . . 121 advance information mc68hc908tv24 ? rev. 2.1 98 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 7.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 7.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 7.8.3 cgmc during break inte rrupts . . . . . . . . . . . . . . . . . . . . . 123 7.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 123 7.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .124 7.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 124 7.9.3 choosing a filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2 introduction this section describes the clock generator module (c gmc). the cgmc generates the crystal clo ck signal, cgmxclk, wh ich operates at the frequency of the crystal. the cgmc also generates the base clock signal, cgmout, which is based on either the cr ystal clock divided by two or the phase-locked l oop (pll) clock, cgmvclk, divided by two. in user mode, cgmout is the clock from which the system integration module (sim) derives the system clocks, including the bus clock, which is at a frequency of cgmo ut divided by two. in monitor mode, ptc3 determines the bus clock. the pll is a fully functional frequency generator designed for use with crystal s or ceramic resonators. the pll can generate an 8-mhz bus frequency using a 32-khz crystal. 7.3 features features of the cgmc include: phase-locked loop with output fr equency in integer multiples of an integer dividend of th e crystal reference low-frequency crystal operati on with low-power operation and high-output frequency resolution programmable prescaler for pow er-of-two increases in frequency programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation clock generator module (cgmc) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 99 automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 7.4 functional description the cgmc consists of th ree major sub-modules: 1. crystal oscillator circuit ? the crystal osc illator circuit generates the constant crystal frequency clock, cgmxclk. 2. phase-locked loop (pll) ? the pll generates the programmable vco frequen cy clock, cgmvclk. 3. base clock selector circuit ? this software-controlled circuit selects either cgmx clk divided by two or the vco clock, cgmvclk, divided by two as t he base clock, cgmout. the sim derives the system clocks from either cgmout or cgmxclk. figure 7-1 shows the struct ure of the cgmc. 7.4.1 crystal oscillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the oscillator ci rcuit works conti nuously even in stop mode so that modules that receive the crystal clock directly, like the timebase module (tbm), can operate in stop mode. the cgmxclk signal is t he output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cg mxclk is then buffered to produce cgmrclk, t he pll reference clock. cgmxclk can be used by other modul es which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50 percent and depends on external factors, in cluding the crystal and related external component s. an externally gen erated clock also can feed the osc1 pin of the crystal oscillator ci rcuit. connect the external clock to the osc1 pin and let the osc2 pin float. advance information mc68hc908tv24 ? rev. 2.1 100 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) figure 7-1. cgmc block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk oscillator (osc) interrupt control pllireq cgmrdv pll analog 2 cgmrclk osc2 osc1 select circuit vddcgm cgmxfc vsscgm lock auto acq vpr1?vpr0 pllie pllf mul11?mul0 reference divider vrs7?vrs0 frequency divider pre1?pre0 to sim, tbm phase-locked loop (pll) a b s* *when s = 1, cgmout = b simdiv2 from sim to sim to sim rds3?rds0 clock generator module (cgmc) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 101 7.4.2 phase-locked loop circuit (pll) the phase-locked loop (pll) circuit is a frequency gener ator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequen cy. the pll can change between acquisition and tracking modes eit her automatically or manually. 7.4.3 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) reference divider frequency prescaler modulo vco fr equency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgm/xfc noise. the vc o frequency is bo und to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cg m/xfc pin changes the frequency within this range. by design, f vrs is equal to the nom inal center-of-range frequency, f nom , (38.4 khz) times a linear fa ctor, l, and a power-of-two factor, e, or (l 2 e )f nom . cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to t he pll through a programmable modulo referenc e divider, which divides f rclk by a factor, r. the di vider?s output is the final referenc e clock, cgmrdv, running at a frequency, f rdv =f rclk /r. with an external crystal (30 khz?100 khz), always se t r = 1 for specified performance. with an external high-frequency clock source , use r to divi de the external frequency to between 30 khz and 100 khz. advance information mc68hc908tv24 ? rev. 2.1 102 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) the vco?s output clock, cgmvcl k, running at a frequency, f vclk , is fed back through a progr ammable prescale divi der and a programmable modulo divider. the prescaler divides the vco clock by a power-of-two factor, p, and the modulo divider reduces the vco clock by a factor, n. the dividers? output is the vco feedb ack clock, cgmvdv, running at a frequency, f vdv =f vclk /(n 2 p ). (see 7.4.6 programming the pll for more information.) the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter then slightly alters t he dc voltage on the external capacitor connected to cgm/xfc based on t he width and direction of the correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 7.4.4 acquisiti on and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency, f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 7.4.4 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vc o. this mode is used at pll startup or when the pll has su ffered a severe noise hit and the vco frequency is far off t he desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 7.6.2 pll bandwidth control register .) tracking mode ? in tracking mode , the filter makes only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the clock generator module (cgmc) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 103 pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 7.4.8 base clock se lector circuit .) the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 7.4.5 manual and automatic pll bandwidth modes the pll can change the bandwidth or oper ational mode of the loop filter manually or automatical ly. automatic mode is recommended for most users. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. (see 7.6.2 pll bandwidth control register .) if pll interrupts are enabled, th e software can wait for a pll interrupt request and then check the lock bit. if interrup ts are disabled, software can poll the lock bit cont inuously (during pll startup, usually) or at periodic intervals. in either case, when the lo ck bit is set, the vco clock is safe to use as the source for the base clock. (see 7.4.8 base clock selector circuit .) if the vco is selected as th e source for the base clock and the lock bit is clear, the pll has suffered a seve re noise hit and the software must take appropriate ac tion, depending on the application. (see 7.7 interrupts for information and precautions on using interrupts.) the following conditions apply when t he pll is in automatic bandwidth control mode: the acq bit (see 7.6.2 pll bandwidth control register .) is a read-only indicator of the mode of the filter. (see 7.4.4 acquisition and tracking modes .) the acq bit is set when the vco fr equency is within a certain tolerance and is cleared when th e vco frequency is out of a certain tolerance. (see 7.9 acquisition/lock time specifications for more information.) advance information mc68hc908tv24 ? rev. 2.1 104 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance and is cleared when th e vco frequency is out of a certain tolerance. (see 7.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 7.6.1 pll control register .) the pll also may operate in ma nual mode (auto = 0). manual mode is used by systems that do not requi re an indicator of the lock condition for proper operation. such syst ems typically operate well below f busmax . these conditions apply when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 7.9 acquisition/lock time specifications .), after turning on the pll by setting pllon in the pll control regi ster (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as th e clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgmc are disabled. 7.4.6 programming the pll this procedure shows how to program the pll. note: the round function in these equations means that the real number should be rounded to t he nearest integer number. clock generator module (cgmc) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 105 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequ ency (four times the desired bus frequency). 3. choose a practical pll (cr ystal) reference frequency, f rclk , and the reference clock divi der, r. typically, the reference crystal is 32.768 khz and r = 1. frequency errors to the pll are corrected at a rate of f rclk /r. for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. the relationship be tween the vco frequency, f vclk , and the reference frequency, f rclk , is p, the power of two multiplier, and n, the range multiplier, are integers. in cases where desired bus fr equency has some tolerance, choose f rclk to a value determined ei ther by other module requirements (such as modules wh ich are clocked by cgmxclk), cost requirements, or ideally, as high as the specified range allows. see section 25. preliminary electrical specifications . choose the reference divider, r = 1. after choosing n and p, the actual bus frequency can be deter mined using equatio n in step 2. when the tolerance on the bus frequency is tight, choose f rclk to an integer divisor of f busdes , and r = 1. if f rclk cannot meet this requirement, use the following equation to solve for r with practical choices of f rclk , and choose the f rclk that gives the lowest r. f vclkdes 4f busdes = f vclk 2 p n r ----------- f rclk () = r round r max f vclkdes f rclk -------------------------- ?? ?? ?? integer f vclkdes f rclk -------------------------- ?? ?? ?? ? ?? ?? ?? = advance information mc68hc908tv24 ? rev. 2.1 106 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 4. select a vco frequency multiplier, n. reduce n/r to the lowest possible r. 5. if n is < n max , use p = 0. if n > n max , choose p using this table: then recalculate n: 6. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 7. select the vco?s powe r-of-two range multipli er e, according to this table: current n value p 0 1 2 3 frequency range e 0 < f vclk < 9,830,400 0 9,830,400 f vclk < 19,660,800 1 19,660,800 f vclk < 39,321,600 2 note: do not program e to a value of 3. n round rf vclkdes f rclk ------------------------------------ - ?? ?? ?? = 0n advance information mc68hc908tv24 ? rev. 2.1 108 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) table 7-1 provides numeric examples . numbers are in hexadecimal notation. 7.4.7 special programming exceptions the programming method described in 7.4.6 programming the pll does not account for three possible exc eptions. a value of 0 for r, n, or l is meaningless when used in the eq uations given. to account for these exceptions: a 0 value for r or n is interpreted exactly the same as a value of 1. a 0 value for l disabl es the pll and prevents its selection as the source for the base clock. see 7.4.8 base clock se lector circuit . 7.4.8 base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the ba se clock, cgmout. the two input clocks go thro ugh a transition control ci rcuit that waits up to three cgmxclk cycles and three cg mvclk cycles to change from one clock source to the other. duri ng this time, cgmout is held in stasis. the output of the transition co ntrol circuit is then divided by two to correct the duty cycle. therefore, the bus clo ck frequency, which is table 7-1. numeric example f bus f rclk rnpel 2.0 mhz 32.768 khz 1 f5 0 0 d1 2.4576 mhz 32.768 khz 1 12c 0 1 80 2.5 mhz 32.768 khz 1 132 0 1 83 4.0 mhz 32.768 khz 1 1e9 0 1 d1 4.9152 mhz 32.768 khz 1 258 0 2 80 5.0 mhz 32.768 khz 1 263 0 2 82 7.3728 mhz 32.768 khz 1 384 0 2 c0 8.0 mhz 32.768 khz 1 3d1 0 2 d0 clock generator module (cgmc) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 109 one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the vco clock c annot be selected as t he base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be tur ned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and th e crystal clock would be forced as the source of the base clock. 7.4.9 cgmc external connections in its typical configur ation, the cgmc require s up to nine external components. five of these are for the crystal osc illator and two or four are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-2 . this figure show s only the logical representation of the internal components and ma y not represent actual circuitry. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines. refer to the crystal manufacture r?s data for more information regarding values for c1 and c2. figure 7-2 also shows the exter nal components for the pll: bypass capacitor, c byp filter network advance information mc68hc908tv24 ? rev. 2.1 110 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) figure 7-2. cgmc exernal connections routing should be done with great care to mini mize signal cross talk and noise. see 25.10.1 cgm component specifications for capacitor and resistor values. 7.5 input/output signals this subsection describes the cgmc i/o signals. 7.5.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 7.5.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. osc1 c 1 c 2 cgmxclk r b x1 r s c byp osc2 cgmxfc v ddcgm note: filter network in box can be replaced with a 0.47- f capacitor, but it will degrade stability. v dd 10 k 0.01 f 0.47 f v sscgm 0.1 f clock generator module (cgmc) input/output signals mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 111 7.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. an external filter netw ork is connected to this pin. (see figure 7-2 .) note: to prevent noise problems, the filter network should be placed as close to the cgmxfc pin as po ssible, with minimum r outing distances and no routing of other sign als across the network. 7.5.4 pll analog power pin (v ddcgm ) v ddcgm is a power pin used by the anal og portions of the pll. connect this pin to the same voltage potential as the v dd pin. note: route v ddcgm carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 7.5.5 pll analog ground pin (v sscgm ) v sscgm is a ground pin used by the anal og portions of the pll. connect this pin to the same voltage potential as the v ss pin. note: route v sscgm carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 7.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal o scillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 7-2 shows only the logical relati on of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequen cy and amplitude of cgmxclk can be unstable at startup. advance information mc68hc908tv24 ? rev. 2.1 112 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.5.7 cgmc base clock output (cgmout) cgmout is the clock out put of the cgmc. this signal goes to the sim, which generates the mcu clocks. cg mout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be eith er the oscillator outpu t, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 7.5.8 cgmc cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 7.6 cgmc registers these registers control and moni tor operation of the cgmc: pll control regist er (pctl) ? see 7.6.1 pll control register pll bandwidth control register (pbwc) ? see 7.6.2 pll bandwidth control register pll multiplier select r egister high (pmsh) ? see 7.6.3 pll multiplier select register high pll multiplier select r egister low (pmsl) ? see 7.6.4 pll multiplier select register low pll vco range se lect register (pmrs) ? see 7.6.5 pll vco range select register pll reference divider sele ct register (pmds) ? see 7.6.6 pll reference divider select register figure 7-3 is a summary of the cgmc registers. clock generator module (cgmc) cgmc registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 113 addr.register name bit 7654321bit 0 $0008 pll control register (pctl) see page 114. read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 $0009 pll bandwidth control register (pbwc) see page 117. read: auto lock acq 0000 r write: reset:00000000 $000a pll multiplier select high register (pmsh) see page 118. read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $000b pll multiplier select low register (pmsl) see page 119. read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 $000c pll vco range select register (pmrs) see page 120. read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 $000d pll reference divider select register (pmds) see page 121. read: 0000 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 7-3. cgmc i/ o register summary advance information mc68hc908tv24 ? rev. 2.1 114 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.6.1 pll control register the pll control register (pctl) contains the in terrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power-of-two range selector bits. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit also is set. pllf always reads as logic 0 when t he auto bit in the pll bandwidth control register (pbwc) is clear . clear the pllf bi t by reading the pll control register. re set clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently cl ear the pllf bit. any re ad or read-modify-write operation on the pll control regi ster clears the pllf bit. address: $0008 bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre0 vpr1 vpr0 write: reset:00100000 = unimplemented figure 7-4. pll cont rol register (pctl) clock generator module (cgmc) cgmc registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 115 pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 7.4.8 base clock selector circuit .) reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, cgmxclk, or the vco clock, cg mvclk, as the source of the cgmc output, cgmout. cgmo ut frequency is one-half the frequency of the select ed clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to the other. du ring the transition, cgmo ut is held in stasis. (see 7.4.8 base clock se lector circuit .) reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. (see 7.4.8 base clock se lector circuit .) pre1 and pre0 ? prescaler program bits these read/write bits control a pre scaler that selects the prescaler power-of-two mult iplier, p. (see 7.4.3 pll circuits and 7.4.6 programming the pll .) pre1 and pre0 cann ot be written when the pllon bit is set. reset clears these bits. note: the value of p is normally 0 when using a 32.768-khz crystal as the reference. advance information mc68hc908tv24 ? rev. 2.1 116 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) vpr1 and vpr0 ? vco power-o f-two range select bits these read/write bits control the vco?s hardware power-of-two range multiplier e that, in conjunction with l, (see 7.4.3 pll circuits , 7.4.6 programming the pll , and 7.6.5 pll vco range select register .) controls the hardware center-of-range frequency, f vrs . vpr1 and vpr0 cannot be written when the pllon bit is set. reset clears these bits. table 7-2. pre 1 a nd pre0 programming pre1 and pre0 p prescaler multiplier 00 0 1 01 1 2 10 2 4 11 3 8 table 7-3. vpr1 and vpr0 programming vpr1 and vpr0 e vco power-of-two range multiplier 00 0 1 01 1 2 10 2 4 11 3 (1) 1. do not program e to a value of 3. 8 note: clock generator module (cgmc) cgmc registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 117 7.6.2 pll bandwidth control register the pll bandwidth contro l register (pbwc): selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset cl ears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is lo cked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. the writ e one function of this bit is reserved for test, so this bit must always be written a 0. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked address: $0009 bit 7654321bit 0 read: auto lock acq 0000 r write: reset:00000000 = unimplemented r = reserved figure 7-5. pll bandwidth control register (pbwc) advance information mc68hc908tv24 ? rev. 2.1 118 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode 7.6.3 pll multiplier select register high the pll multiplier select regist er high (pmsh) contains the programming information for the high byte of t he modulo feedback divider. mul11?mul8 ? multip lier select bits these read/write bits control the high byte of the modulo feedback divider that selects the vco frequency multiplier n. (see 7.4.3 pll circuits and 7.4.6 programming the pll .) a value of $0000 in the multiplier select regi sters configures the mo dulo feedback divider the same as a value of $ 0001. reset initializes t he registers to $0040 for a default multiply value of 64. address: $000a bit 7654321bit 0 read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 = unimplemented figure 7-6. pll multiplier se lect register high (pmsh) clock generator module (cgmc) cgmc registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 119 note: the multiplier select bits have built-in pr otection such that they cannot be written when the pll is on (pllon = 1). pmsh7?pmsh4 ? unimplemented bits these bits have no function and always read as logic 0s. 7.6.4 pll multiplier select register low the pll multiplier se lect register low (pmsl) contains the programming information for the low byte of the modulo feedback divider. mul7?mul0 ? multiplier select bits these read/write bits control the low byte of the modulo feedback divider that selects the vco frequency multiplier, n. (see 7.4.3 pll circuits and 7.4.6 programming the pll .) mul7?mul0 cannot be written when the pllon bit in the pc tl is set. a value of $0000 in the multiplier select regi sters configures the mo dulo feedback divider the same as a value of $00 01. reset initializes t he register to $40 for a default multiply value of 64. note: the multiplier select bits have built-in pr otection such that they cannot be written when the pll is on (pllon = 1). address: $000b bit 7654321bit 0 read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:01000000 figure 7-7. pll multiplier se lect register low (pmsl) advance information mc68hc908tv24 ? rev. 2.1 120 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.6.5 pll vco range select register note: pmrs may be called pvrs on other hc08 derivatives. the pll vco range select register (pmrs) cont ains the programming information required fo r the hardware confi guration of the vco. vrs7?vrs0 ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier l which, in conjunction with e (see 7.4.3 pll circuits , 7.4.6 programming the pll , and 7.6.1 pll control register .), controls the hardware ce nter-of-range frequency, f vrs . vrs7?vrs0 cannot be written when the pllon bi t in the pctl is set. (see 7.4.7 special programming exceptions .) a value of $00 in the vco range select regist er disables the pll and cl ears the bcs bit in the pll control register (pctl). (see 7.4.8 base clock selector circuit and 7.4.7 special programming exceptions .). reset initializes the register to $40 fo r a default range mult iply value of 64. note: the vco range select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1) and such that the vco clock cannot be selected as the source of the base cloc k (bcs = 1) if the vco range select bits are all clear. the pll vco range select register must be pr ogrammed correctly. incorrect programming can result in failure of the pll to achieve lock. address: $000c bit 7654321bit 0 read: vrs7 vrs6 vrs5 vrs4 vrs3 vrs2 vrs1 vrs0 write: reset:01000000 figure 7-8. pll vco range select register (pmrs) clock generator module (cgmc) cgmc registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 121 7.6.6 pll reference divider select register note: pmds may be called prds on other hc08 derivatives. the pll reference divider select register (pmds) contains the programming information for t he modulo reference divider. rds3?rds0 ? reference divider select bits these read/write bits control the modul o reference divider that selects the reference division factor, r. (see 7.4.3 pll circuits and 7.4.6 programming the pll .) rds7?rds0 cannot be written when the pllon bit in the pctl is set. a va lue of $00 in the reference divider select register configur es the reference divider the same as a value of $01. (see 7.4.7 special progr amming exceptions .) reset initializes the register to $01 for a default divide value of 1. note: the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). note: the default divide value of 1 is recommended for all applications. pmds7?pmds4 ? unimplemented bits these bits have no function and always read as logic 0s. address: $000d bit 7654321bit 0 read: 0000 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented figure 7-9. pll reference divi der select register (pmds) advance information mc68hc908tv24 ? rev. 2.1 122 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the p ll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock fr equency is corrupt, and appropriate precautions should be taken. if the a pplication is not fr equency sensitive, interrupts should be disabled to prev ent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the p ll is not locked (lock = 0). therefore, software should make sure the pll is lo cked before setting the bcs bit. 7.8 special modes the wait instruction pu ts the mcu in low pow er-consumption standby modes. 7.8.1 wait mode the wait instruction does not affect the cgmc. before en tering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl) to save power. less power-sensitive applications can dise ngage the pll wit hout turning it off, so that the pll cl ock is immediately availa ble at wait exit. this would be the case also when the pll is to wa ke the mcu from wait clock generator module (cgmc) acquisition/lock time specifications mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 123 mode, such as when the pll is first enabled and wait ing for lock or lock is lost. 7.8.2 stop mode the stop instruction dis ables the phase-locked loop but the oscillator will continue to operate. if the stop instruction is execut ed with the vco clock, cgmvclk, divided by two driving cg mout, the pll automatic ally clears the bcs bit in the pll control regi ster (pctl), thereby sele cting the crystal clock, cgmxclk, divided by two as the so urce of cgmout . when the mcu recovers from stop, th e crystal clock divided by two drives cgmout and bcs remains clear. 7.8.3 cgmc during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. (see 20.8.3 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect the pllf bit dur ing the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write the pll control register during the break state without affecting the pllf bit. 7.9 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times. advance information mc68hc908tv24 ? rev. 2.1 124 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) 7.9.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time, within specified tolera nces, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the ou tput settles to the desi red value plus or minus a percent of the frequen cy change. therefore, t he reaction time is constant in this definit ion, regardless of the si ze of the step input. for example, consider a system with a 5 percent acqui sition time tolerance. if a command instruct s the system to change from 0 hz to 1 mhz, the acquisition time is the time ta ken for the frequency to reach 1mhz 50 khz. fifty khz = 5% of the 1-mh z step input. if the system is operating at 1 mhz and suff ers a ?100-khz noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. 7.9.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time. the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these clock generator module (cgmc) acquisition/lock time specifications mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor clock generator module (cgmc) 125 corrections. this parameter is under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 7.4.3 pll circuits , 7.4.6 programming the pll , and 7.6.6 pll reference divider select register .) another critical parameter is th e external filter network. the pll modifies the voltage on the vco by adding or subtracting charge from capacitors in this network. therefore, the rate at wh ich the voltage changes for a given frequency erro r (thus change in charge) is proportional to the capacitance. the size of the capacitor also is related to the stability of the pll. if the c apacitor is too sma ll, the pll cannot make small enough adjus tments to the volt age and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see 7.9.3 choosing a filter .) also important is the operatin g voltage potential applied to v ddcgm . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor, filter capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination. 7.9.3 choosing a filter as described in 7.9.2 parametric in fluences on re action time , the external filter network is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. advance information mc68hc908tv24 ? rev. 2.1 126 clock generator module (cgmc) freescale semiconductor clock generator module (cgmc) either of the filter networks in figure 7-10 is recommended when using a 32.768-khz reference crystal. figure 7-10 (a) is used for applications requiring better stability. figure 7-10 (b) is used in low-cost applications where stability is not critical. figure 7-10. pll filter cgmxfc 10 k 0.01 f 0.47 f v sscgm cgmxfc 0.47 f v sscgm (a) (b) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 127 advance information ? mc68hc908tv24 section 8. closed-caption data slicer (dsl) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 8.4.1 slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.4.2 line and field de tection. . . . . . . . . . . . . . . . . . . . . . . . . . .129 8.4.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.2 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.5.3 debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 8.6 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.6.1 video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.6.2 vsync, hsync, and video input require ments . . . . . . . 132 8.7 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 8.7.1 dsl character registers . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.7.2 dsl control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.7.3 dsl control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.7.4 dsl status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.9 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 advance information mc68hc908tv24 ? rev. 2.1 128 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) 8.2 introduction the closed-caption data slicer (dsl) extracts fcc (federal communications commission) closed- caption compatible data from an ntsc (national television system committee) or pal (phase alternating line) composite vi deo signal for closed-caption and extended data services applications. 8.3 features the dsl provides these features: fcc/eia-744 v-chip compatible fcc/eia-608 line 21 format data extraction on both field 1 and field 2 software programmable line selection hardware parity checking software programmable data slicing level 8.4 functional description the closed-caption data slicer (dsl ) extracts fcc closed-caption compatible data from an ntsc composite video signal. the dsl accomplishes this task by slicing sync and data info rmation from the incoming video; the sync information is used to locate fields and lines to trigger data sampling, and the sampled sliced data is stored in registers for cpu access. a block diagram of the dsl is shown in figure 8-1 . 8.4.1 slicer the slicer circuitry compares the co mposite video input with internal reference levels to determine when sync pulses or data bits are being received. dsl control bits allow the us er to select one of four reference levels for slicing data. refer to figure 8-2 . closed-caption data slicer (dsl) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 129 8.4.2 line and field detection the line and field detection circuitry uses the s eparated sync output of the slicer section, along with signals der ived from the hsync and vsync inputs, to determi ne line and field timing for the dsl and field timing for the on-scr een display module (osd). dsl control registers enable the user to select one of severa l lines from which to extract data in closed-caption format, and also provide flexibility for adapting to differences in chassis syn c and video signal timing. figure 8-1. data slicer block diagram decode line and fields detection data sampler slicer registers pll video osd dslcr1 dslcr2 dslch1 dslch2 dslsr hc08 internal bus addr/control data interrupt field sync trigger data clocks sync closed caption data slicer advance information mc68hc908tv24 ? rev. 2.1 130 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) figure 8-2. slicer input and output 8.4.3 data sampling the data sampling circuitry uses the frequency reference from the pll (phase locked to the hsy nc input) to sample data bits from the separated data output of the slicer section. the sampling circuitry performs parity checking and stores the data in parallel format in registers which the cpu can access. the dsl sets a status register bit (dsfl) and optionally w ill generate an interrupt to indicate when data is available. 8.5 programming guidelines the dsl can be used for extracting data in the fcc closed-caption format from both fiel ds in the composite vi deo signal. the dsl may be configured to search for data on any line from 14 to 29 (vsync timing may limit this range in so me applications), although it cannot search on multiple lines. the dsl does not perform any clos ed-caption decoding or display; these functions must be provided in software with support of the osd module. data slicing level, selectable blanking clamped to v dd /2 (2.5 v) sync slicing level, fixed composite video in separated sync out separated data out closed-caption data slicer (dsl) programming guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 131 8.5.1 setup the dsl control registers 1 and 2 must be initialized for proper operation. the dsen bit in dslcr1 should be set to enable the dsl, and the dsien bit should be set if the dsfl will be serviced through interrupts rather than polling. the desired line for decoding data should be specified in dslcr1, and the data slicing voltage reference, vertical pulse width and de lay should be initialized in dslcr2. some of these control bits may requi re adjustment during ope ration if video input conditions change. 8.5.2 interrupt servicing in both the interrupt and polling methods, the ds fl flag in the dslsr indicates that two bytes are availabl e for reading. the field1 bit in the dslsr indicates which field the 2 bytes have been extracted from. the ovfl bit should also be checked to ensure that overflow has not occurred. within the service routine, dsfl should be cleared by writing to the dslsr. since the two character registers are shared for both fi eld 1 and field 2, the user has approximat ely one video vertical sc an (16.68 ms) to unload two bytes of data per fi eld. the two bytes each contain a 7-bit code and a parity error flag. the parit y error flags i ndicate that th e data received may be invalid. 8.5.3 debugging the dslsr status bits can be helpful when us ing the dsl in a new application. if the dsl does not correctly slic e data, check these status bits in this order: 1. csync ? this bit prov ides visibility of th e separated sync output of the slicer section. if csync is not set duri ng the time that a sync pulse is present in the incoming video, then the input level of the video signal needs adjus tment to allow pr oper sync slicing. 2. vpdet ? this bit indicates that a wide vertical sync pulse has been detected in the comp osite video. if vpdet is not set after the advance information mc68hc908tv24 ? rev. 2.1 132 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) vertical blanking interval , this indicates that either the wide vertical sync pulses in the composite vi deo are shorter than the pulse width defined by pw1:pw0, or the vsync input was not active during the vertical blanking interval , or the selected decoding line was encountered before the vertic al sync was seen in composite video or vsync. 3. ric1 and ric0 ? these two bits ar e the output of a counter that counts up to three rising edges in the sliced data during the run-in-clock window. if the count is less than three, this may indicate that the incorrect line is being decoded, or t hat there is too much delay between co mposite video and hsync. 8.6 input/output the dsl has one dedicated pi n, the video input. it also uses the vsync and hsync i nputs indirectly. 8.6.1 video this dedicated input provi des the ntsc or pal composite video signal from the external video system. the closed-caption data and sync information is extracted from this signal. a typi cal input circuit for the closed-caption video input is shown in figure 8-3 . the video input uses a sync versus blanking level duty cycle clamp to set the blanking level of the incoming video to v dd divided by two. 8.6.2 vsync, hsync, and video input requirements the dsl uses both vsync and hsync indirectly, putting some restrictions on the relationship between these two signals and the composite video. refer to figure 8-4 . closed-caption data slicer (dsl) input/output mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 133 figure 8-3. video input circuit figure 8-4. dsl input timing the external vsync input is provi ded by the osd to the dsl as an active-high signal. vsync is used by the dsl to: detect a valid vertic al blanking interval generate field informat ion for the dsl and osd video +5 v to video pin 1 f/15 v 82 pf 2k7 3 k 1 v pp * drive z 0 < 100 ? * from negative synchronous tip to 100 ire video vsync a: rising edge csync first wide vertical pulse to rising edge vsync ? minimum 1 s b: vsync pulse width ? minimum 2 s c: rising edge vsync to rising edge csync of line to be detected ? minimum 64 s a b c advance information mc68hc908tv24 ? rev. 2.1 134 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) a synthesized version (50 percent duty cycle) of external hsync is provided by the pll to the dsl. the dsl also uses higher frequency pll derivatives of hsync for most of its synchr onization. the horizontal frequency is used to generate fi eld information for the osd. the video input is separated in to sync and data components. composite sync (both vert ical and horizontal sync information) is used by the dsl to: detect a valid vertic al blanking interval disable the video input clam p during vertic al blanking generate field info rmation for the dsl latch an overflow condition indicate when the desired decoding line has been found composite data is used fo r detecting the run-in-clo ck, the star t bit, and sampling the data. 8.7 registers the dsl has five registers, which are described in this section. dsl character register 1, dslch1 dsl character register 2, dslch2 dsl control register 1, dslcr1 dsl control register 2, dslcr2 dsl status register, dslsr closed-caption data slicer (dsl) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 135 8.7.1 dsl character registers these registers, dslch1 and dslch2, each contain seven data bits and a parity error flag. pe ? parity error bit this read-only bit is set when odd par ity is not detected on the byte received. writing to the dsl status registers clears this bit. a reset also clears this bit. da6?da0 ? closed-c aption data bit these read-only bits are sampled (lsb first) from the data slicer, which extracts data from the video in put pin. these seven bits will define a closed-caption char acter. a reset has no effect on these bits. address: $0047?$0048 bit 7654321bit 0 read: pe da6 da5 da4 da3 da2 da1 da0 write: reset:0xxxxxxx = unimplemented x = indeterminate figure 8-5. dsl character registers (dslch1 and dslch2) advance information mc68hc908tv24 ? rev. 2.1 136 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) 8.7.2 dsl control register 1 dsien ? data slicer interrupt enable bit dsien determines if the dsfl bi t in the dslsr is enabled to generate interrupt requests to the cpu. a reset clears this bit. 1 = dsfl interrupt enabled 0 = dsfl interrupt disabled dsen ? data slicer enable bit dsen determines if the dsl is enabled. when the dsl is enabled, the data slicer volt age reference is tur ned on and the pll clock outputs are input to the dsl circ uitry. the pll must be enabled (pllen bit on the osd enab le control register) to operate the dsl. the dsl provides field informati on to the osd and should not be disabled if the osd is in us e. a reset clears this bit. 1 = dsl enabled 0 = dsl disabled vven ? vsync veri fication enable bit vven determines if vsy nc from the osd modul e will be checked during the vertical blanking interval . vven set allows data extraction abortion if vsync is not detected. address: $0049 bit 7654321bit 0 read: dsien dsen vven line4 line3 line2 line1 disclp write: reset:00000000 figure 8-6. dsl contro l register 1 (dslcr1) closed-caption data slicer (dsl) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 137 line4?line1 ? closed- caption line bits these four bits allow the user to specify the line to be used for closed-caption decoding, according to table 8-1 . a reset clears these bits. disclp ? disable cl amping in test mode this bit can be ac cessed only in dsl test mode, which is activated by setting bit dsltst of the osd status register ($0046). it allows direct control over an internal signal that controls the ana log portion of the data slicer. it is provided to facilitate the producti on test of the slicer circuit. table 8-1. line selection line4?line1 target line 0000 14 0001 15 0010 16 ?? 1101 27 1110 28 1111 29 advance information mc68hc908tv24 ? rev. 2.1 138 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) 8.7.3 dsl control register 2 vr1 and vr0 ? volt age reference bits these bits select the reference bias voltage for slicing data according to table 8-2 . as seen in figure 8-8 , the input blanking level is clamped to 2.5 v, and the sync slicing level is fi xed at 2.4 v. a reset clears these bits. address: $004a bit 7654321bit 0 read: vr1 vr0 pw1 pw0 vpd syncmp datcmp blkcmp write: reset:00000000 = unimplemented figure 8-7. dsl contro l register 2 (dslcr2) table 8-2. data slicer bias voltage vr1 vr0 nominal bias 0 0 2.80 v 0 1 2.74 v 1 0 2.66 v 1 1 2.60 v closed-caption data slicer (dsl) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 139 figure 8-8. data and sync slicing pw1 and pw0 ? vertical sync pulse width bit these bits define, according to table 8-3 , the minimum width of an extracted sync signal pulse required to identify it as a vertical sync pulse. the standard video ve rtical sync interval pulse width is 29.2 s; the dsl requires at least 8 s to recognize a ve rtical sync pulse. a reset clears these bits. data slicer bias video 1 v pp sliced data sliced sync v and h 2.4 vdc - + - + data slicer bias blanking clamped to v dd /2 (2.5 v) sync slicing level 2.4 v 50 ire ?40 ire 0.357 v 0.643 v table 8-3. minimum vertical pulse width pw1 pw0 pulse width 00 8 s 01 10 s 10 12 s 11 14 s advance information mc68hc908tv24 ? rev. 2.1 140 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) vpd ? vertical pulse delay bit vpd determines whether the vsync input is delayed before field detection. vpd should be set when the vsync ac tive edge is within 4 s of the hsync active edge for either field. see figure 8-9 for clarification. a reset clears this bit. 1 = vsync input is delayed by 12 to 22 s before field detection 0 = vsync input is not delayed syncmp ? synchronism slicin g comparator output bit out of test mode, this read-only bit is always 0. in dsl test mode, which is activated by setting bit dsltst of th e osd status register ($0046), it mirrors the state of the synchronism slicing comparator. it is provided to facilitate the production test of the data slic er circuit. datcmp ? data slicing co mparator output bit this bit is also meaningful only in dsl test mode . it mirrors the state of the data slicing comparator. blkcmp ? blanking level comparator output bit this bit is also meaningful only in dsl test mode . it mirrors the state of the blanking le vel comparator. figure 8-9. conditions for se tting vertical pulse delay vsync hsync field1 hsync field2 b a internally delayed vsync (vpd = 1) if |a| < 4 s or |b| < 4 s, set vpd = 1 closed-caption data slicer (dsl) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor closed- caption data slicer (dsl) 141 8.7.4 dsl status register the dslsr contains the dsl interrupt flag and status bi ts and provides visibility to the slicer sync output. dsfl ? data sampled flag bit this bit is set to indicate that the dsl has sampled 16 bits of closed-caption data (inc luding parity) and plac ed them in dslch1 and dslch2. it will cause an interr upt if the dsien bit in dslcr1 is set. it is cleared by writing to t he dslsr. a reset also clears this bit. ovfl ? data overflow bit this bit is set when new data starts to be ex tracted and dsfl is still set from the previous field. this condition does not cause an interrupt. it is cleared by writing to the dslsr. a reset also clears this bit. field1 ? field 1 indicator bit this bit indicates which field the closed-caption data in dslch1 and dslch2 was extracted fr om. a logic 1 indicates that the data in the status and character registers co rrespond to information retrieved from the specified line in field 1. a logic 0 indi cates that the register contents correspond to information retr ieved from the specified line in field 2. a reset clears this bit. address: $004b bit 7654321bit 0 read: dsfl ovfl field1 0 csync vpdet ric1 ric0 write: reset:0000x000 = unimplemented figure 8-10. dsl stat us register (dslsr) advance information mc68hc908tv24 ? rev. 2.1 142 closed-caption data slicer (dsl) freescale semiconductor closed-caption data slicer (dsl) csync ? composite s eparated sync bit this bit reflects the current stat e of the separat ed sync signal. if csync = 1, it indicates the presence of a vertical or horizontal sync pulse in the composit e video input. if csync = 0, no sync pulse is currently present in the composite video input. a rese t has no effect on this bit. vpdet ? vertical sync pulse detect bit this bit is set when a vsy nc rising edge is found in the interval that starts in the valid vertical sync pulse detection and finishes one line before the programmed line to be extracted. ric1 and ric0 ? run-in clock cycle count bot these bits reflect the current state of a 2-bit run-in clock cycle counter. this counter triggers off of the positive transiti ons of the video signal in an 8 s wide window starting 24 s after the horizontal sync pulse of the specified line. if both bits are set, this indicates that at least three positive transitions were det ected. these bits are cleared by writing to the dslsr. a rese t also clears these bits. 8.8 low-power modes the dsl remains active during wait mode or stop mode; however, it will be unable to interrupt the cpu and bring it out of these modes. it is recommended that the dsl be disabled during wait mode or stop mode. 8.9 interrupts and resets the dsl?s only source of interrupt is the dsfl flag in the dslsr. this interrupt is enabled by the dsien bit in the dslcr1. this interrupt will cause the mcu to vector to the address stored in $ffec?$ffed. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor configuration register (config) 143 advance information ? mc68hc908tv24 section 9. configuration register (config) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.2 introduction this section describes the config uration register (config). the configuration register enables or disables these options: stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 cgmxclk cycles) stop instruction computer operating pr operly module (cop) low-voltage inhi bit (lvi) module control and voltage trip point selection 9.3 functional description the configuration register is used in the initialization of various options. it can be written only once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the mcu, it is recomm ended that this r egister be written immediately after reset. the configurat ion register is located at $000e. it may be read at anytime. note: on a flash device, the options e xcept lvi5or3 are one-time writable by the user after each re set. the lvi5or3 bit is one-time writable by the advance information mc68hc908tv24 ? rev. 2.1 144 configuration register (config) freescale semiconductor configuration register (config) user only after each por (power-on re set). the config register is not in the flash memory but is a special register containing one-time writable latches after each reset. up on a reset, the config register defaults to predetermined settings as shown in figure 9-1 . lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, se tting the lvistop bit enables the lvi to operate during stop mode . reset clears lvistop. see section 15. low-vol tage inhibit (lvi) . 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operati ng mode of the lvi module. see section 15. low-vol tage inhibit (lvi) . the voltage mode selected for the lvi should ma tch the operating v dd . see section 25. preliminary electri cal specifications for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode. 0 = lvi operates in 3-v mode. lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see section 15. low-voltage inhibit (lvi) . 1 = lvi module resets disabled 0 = lvi module resets enabled address: $000e bit 7654321bit 0 read: lvistop lvi5or3 ? lvirstd lvipwrd ssrec coprs stop copd write: reset:00000000 note: lvi5or3 bit is only re set via por (power-on reset) figure 9-1. configurat ion register (config) configuration register (config) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor configuration register (config) 145 lvipwrd ? lvi power disable bit lvipwrd disables t he lvi module. see section 15. low-voltage inhibit (lvi) . 1 = lvi module power disabled 0 = lvi module power enabled ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmx clkc cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscill ator, do not se t the ssrec bit. note: when the lvistop is enabled, the system stabilization time for power on reset and long stop recovery ( both 4096 cgmxclk cycles) gives a delay longer than the enable time fo r the lvi. there is no period where the mcu is not protecte d from a low-power c ondition. however, when using the short stop recovery conf iguration option, the 32-cgmxclk delay is less than the lv i?s turn-on time and ther e exists a period in startup where the lvi is not protecting the mcu. coprs ? cop rate select bit coprs selects the cop timeout per iod. reset clear s coprs. see section 10. computer o perating properly (cop) . 1 = cop timeout period = 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 ? 2 4 cgmxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. see section 10. computer operating properly (cop) . 1 = cop module disabled 0 = cop module enabled advance information mc68hc908tv24 ? rev. 2.1 146 configuration register (config) freescale semiconductor configuration register (config) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor computer operating properly (cop) 147 advance information ? mc68hc908tv24 section 10. computer operating properly (cop) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 10.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 150 10.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 152 10.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. advance information mc68hc908tv24 ? rev. 2.1 148 computer operating properly (cop) freescale semiconductor computer operating properly (cop) 10.3 functional description figure 10-1 shows the structure of the cop module. figure 10-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles, depending on the state of the co p rate select bit, coprs, in the configurat ion register. with a 2 13 ?2 4 cgmxclk cycle overflow option, a 32. 768-khz crystal gives a cop timeout period of 250 ms. writing any value to locati on $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write cgmxclk reset vector fetch reset circuit reset status register internal reset sources clear stages 5?12 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction from config cop rate sel from config computer operating properly (cop) i/o signals mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor computer operating properly (cop) 149 a cop reset pulls the rst pin low for 32 cgm xclk cycles and sets the cop bit in the reset st atus register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 10.4 i/o signals the following paragraphs descri be the signals shown in figure 10-1 . 10.4.1 cgmxclk cgmxclk is the crystal oscillator output si gnal. cgmxclk frequency is equal to the crystal frequency. 10.4.2 stop instruction the stop instruction cl ears the cop prescaler. 10.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 10.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 10.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. advance information mc68hc908tv24 ? rev. 2.1 150 computer operating properly (cop) freescale semiconductor computer operating properly (cop) 10.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 10.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 10.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration register. see section 9. config uration register (config) . 10.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configurat ion register. see section 9. confi guration register (config) . 10.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: writing clears cop counter, any value reset: unaffected by reset figure 10-2. cop contro l register (copctl) computer operating properly (cop) interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor computer operating properly (cop) 151 10.6 interrupts the cop does not generate cpu interrupt requests. 10.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. 10.8 low-power modes the wait and stop instruct ions put the mcu in low power-consumption standby modes. 10.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 10.8.2 stop mode stop mode turns off t he input clock to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction disabled, exec ution of a stop instruct ion results in an illegal opcode reset. advance information mc68hc908tv24 ? rev. 2.1 152 computer operating properly (cop) freescale semiconductor computer operating properly (cop) 10.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 153 advance information ? mc68hc908tv24 section 11. central processor unit (cpu) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.5 arithmetic/logic unit (alu ) . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 11.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 11.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. advance information mc68hc908tv24 ? rev. 2.1 154 central processor unit (cpu) freescale semiconductor central processor unit (cpu) 11.3 features features include: object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64 kbytes low-power stop and wait modes central processor unit (cpu) cpu registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 155 11.4 cpu registers figure 11-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 11-1. cpu registers 11.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 11-2. a ccumulator (a) advance information mc68hc908tv24 ? rev. 2.1 156 central processor unit (cpu) freescale semiconductor central processor unit (cpu) 11.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 11-3. index register (h:x) central processor unit (cpu) cpu registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 157 11.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 11-4. stack pointer (sp) advance information mc68hc908tv24 ? rev. 2.1 158 central processor unit (cpu) freescale semiconductor central processor unit (cpu) 11.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 11-5. progr am counter (pc) central processor unit (cpu) cpu registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 159 11.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag bit the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag bit the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-c arry (add) or add-with-carry (adc) op eration. the half-carry flag is required for binary-coded decimal (bcd) arit hmetic operations. the daa instruction uses the st ates of the h and c fl ags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask bit when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 11-6. condition code r egister (ccr) advance information mc68hc908tv24 ? rev. 2.1 160 central processor unit (cpu) freescale semiconductor central processor unit (cpu) automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cpu registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag bit the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag bit the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag bit the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 central processor unit (cpu) arithmetic/logic unit (alu) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 161 11.5 arithmetic/logic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 11.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 11.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 11.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. advance information mc68hc908tv24 ? rev. 2.1 162 central processor unit (cpu) freescale semiconductor central processor unit (cpu) 11.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) instruction set summary mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 163 11.8 instruction set summary table 11-1. instruction se t summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 c b0 b7 0 b0 b7 c advance information mc68hc908tv24 ? rev. 2.1 164 central processor unit (cpu) freescale semiconductor central processor unit (cpu) bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 table 11-1. instruction se t summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) instruction set summary mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 165 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 table 11-1. instruction se t summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc advance information mc68hc908tv24 ? rev. 2.1 166 central processor unit (cpu) freescale semiconductor central processor unit (cpu) dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 11-1. instruction se t summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) instruction set summary mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 167 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp ) ? 1 ??????inh 87 2 pshh push h onto stack push (h) ; sp (sp ) ? 1 ??????inh 8b 2 pshx push x onto stack push (x) ; sp (sp ) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 table 11-1. instruction se t summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 c b0 b7 b0 b7 c advance information mc68hc908tv24 ? rev. 2.1 168 central processor unit (cpu) freescale semiconductor central processor unit (cpu) rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 table 11-1. instruction se t summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) opcode map mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor central processor unit (cpu) 169 11.9 opcode map see table 11-2 . tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 11-1. instruction se t summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc advance information mc68hc908tv24 ? rev. 2.1 170 central processor unit (cpu) freescale semiconductor central processor unit (cpu) table 11-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 171 advance information ? mc68hc908tv24 section 12. user flash memory 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 12.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.5 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 12.5.1 flash charge pump frequency control . . . . . . . . . . . . . 175 12.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 12.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . 178 12.8 user flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . 181 12.9 user flash block protect register . . . . . . . . . . . . . . . . . . . .182 12.10 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.11 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.2 introduction this section describes the operation of the embedded user flash memory. this memory ca n be read, programmed, and erased from a single external supply . the program, erase, a nd read operations are enabled through the use of an internal charge pump. 12.3 functional description the user flash memory is an array of 24,064 bytes with an additional 22 bytes of user vectors and two byte s for block protection. an erased bit reads as logic 0 and a programmed bit reads as a logic 1. program and erase operations are facilitated through cont rol bits in a memory mapped register. details for these operations appear la ter in this section. advance information mc68hc908tv24 ? rev. 2.1 172 user flash memory freescale semiconductor user flash memory memory in the user fla sh array is organized in to pages within rows. there are eight pages of memory per row with eight bytes per page. the minimum erase block size is a singl e row, 64 bytes. programming is performed on a per page basis; eight bytes at a time. the address ranges for the user me mory and vectors are: $a000?$fdff; user memory $ff80?$ff81; block protect registers $ffea?$ffff; locations reserved for user-defined interrupt and reset vectors when programming the flash , just enough program ti me must be used to program a page. too much program time c an result in a program disturb condition, in which ca se an erased bit on the row being programmed becomes unintentionally programmed. progr am disturb is avoided by using an it erative program and marg in read technique known as the smart page programming algorithm. the smart programming algorithm is required whenever programming the array (see 12.7 flash program/margin read operation ). to avoid the program disturb issue, each row should not be programmed more than eight times before it is erased. the eight program cycle maximum per row aligns with the architecture?s eight pages of storage per row. the margin re ad step of the smart pr ogramming algorithm is used to ensure programmed bits are programmed to sufficient margin for data retention over the device lifetime. row architecture for this array is: $a000?$a03f; row 0 $a040?$a07f; row 1 $a080?$a0bf; row 2 --------------- ------------- $ffc0?$ffff; row 383 user flash memory flash control register mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 173 programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 12.4 flash control register the user flash cont rol register ( fl1cr) controls flash program, erase, and margin read operations. fdiv1 ? frequency di vide control bit this read/write bit together with fdiv0 selects the value by which the charge pump clock is divided fr om the system clock. see 12.5.1 flash charge pump frequency control . fdiv0 ? frequency di vide control bit this read/write bit together with fdiv1 selects the value by which the charge pump clock is divided fr om the system clock. see 12.5.1 flash charge pump frequency control . blk1 ? block erase control bit this read/write bit together with blk0 allows erasing of blocks of varying size. see 12.6 flash erase operation for a description of available block sizes. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficul t for unauthorized users. address: $fe07 bit 7654321bit 0 read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 figure 12-1. user flash control register (fl1cr) advance information mc68hc908tv24 ? rev. 2.1 174 user flash memory freescale semiconductor user flash memory blk0 ? block erase control bit this read/write bit together with blk1 allows erasing of blocks of varying size. see 12.6 flash erase operation for a description of available block sizes. hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and the proper sequence for program/margin read or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off margin ? margin read control bit this read/write bit confi gures the memory for ma rgin read operation. margin cannot be set if the hven = 1. margin will return to unset automatically if asse rted when hven is set. 1 = margin read operation selected 0 = margin read oper ation unselected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked wit h the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected user flash memory charge pump mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 175 12.5 charge pump the internal flash charge pump is an analog circuit that provides the proper voltage to the flash memory when reading, pr ogramming, and erasing the memory arrays. only one charge pump circuit services both flash memories. 12.5.1 flash charge pump frequency control the internal charge pump required for program, margin read, and erase operations is designed to operate most efficiently with a 2-mhz clock. the charge pump clock is der ived from the bus clock. table 12-1 shows how the fdiv bits are used to select a charge pump frequency based on the bus clock frequency. program and erase o perations cannot be performed if the bus clock frequency is below 2 mhz. . note: since only one charge pump circui t services both flash arrays, the actual fdiv bits received by the c harge pump are the logical or of the individual fdiv bits of registers fl1cr and fl2cr. table 12-1. charge pump clock frequency fdiv1 fdiv0 pump clock frequency bus clock frequency 0 0 bus frequency 1 1.8 to 2.5 mhz 0 1 bus frequency 2 3.6 to 5.0 mhz 1 0 bus frequency 2 3.6 to 5.0 mhz 1 1 bus frequency 4 7.2 to 10.0 mhz advance information mc68hc908tv24 ? rev. 2.1 176 user flash memory freescale semiconductor user flash memory 12.6 flash erase operation use the following procedure to erase a block of flash memory (to read as logic 0). values for the ti me parameters ar e specified in 25.11 memory characteristics . 1. set the erase bit, the blk0, blk1, fdiv0, and fdiv1 bits in the user flash c ontrol register ($fe07). see table 12-1 for fdiv settings. see table 12-2 for block sizes. 2. ensure that the block to be erased is not protected by the settings in the fl1bpr register. read the fl1b pr register. if test voltage, v tst , is applied to the irq pin, block protection is bypassed. this bypass is useful when the enti re array (incl uding the fl1bpr register) needs to be erased. see 12.9 user flash block protect register . 3. write to any flash address wi th any data within the block address range desire d. if the address is in a protected area, the erase bit will be clear ed and the following st eps of the erase procedure are blocked. 4. set the hven bit. 5. wait for a time, t erase . 6. clear the hven bit. 7. wait for a time, t kill , for the high voltages to dissipate. 8. clear the erase bit. 9. after a time, t hvd , the memory can be a ccessed again in read mode. note: while these operations mu st be performed in th e order shown, other unrelated operations may occur betw een the steps. do not exceed t erase maximum. table 12-2 shows the various block si zes which can be erased in one erase operation. user flash memory flash erase operation mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 177 in step 3 of the eras e operation, the desired erase addresses are latched and used to determine the lo cation of the block to be erased. for the full array (blk1 = blk0 = 0), the only requirement is that the user flash memory is selected. writing to an y address in the r ange $a000 to $fdff or the vectors in the address rang e $ffea to $ffff will enable the full array erase. in the ?upper 2/3 array? case in table 12-2 (blk1 = 0, blk0 = 1), the state of a 15 :a 14 = 11 determines t hat the range from $c000 to $fdff and $ffea to $ffff is erased. for example, writing to address $d123 will erase the range $c000 to $fdff and $ffea to $ffff. in the ?lower 1/3 arra y? case (blk1 = 0, bl k0 = 1), the state of a 15 :a 14 = 10 determines that the range from $a000 to $bfff is erased. for example, writing to address $b123 will er ase the range $a000 to $bfff. in the ?eight row case? (blk1 = 1, blk0 = 0), 512- byte blocks are erased as determined by upper addresses a 15 ?a 9 . for example, writing to address $fb10 will erase t he range $fa00 to $fbff. in the ?single row case? (blk1 = 1, blk0 = 1), 64-byte blocks are erased as determined by upper addresses a 15 ?a 6 . for example, writing to address $bc60 will erase the range $bc40 to $bc7f. table 12-2. erase block sizes write to address bits address value blk1 blk0 desired erase address range array size any flash address any 0 0 $a000?$fdff and $ffea?$ffff full array: 24 kbytes a 15 :a 14 11 0 1 $c000?$fdff and $ffea?$ffff upper 2/3 array: 16 kbytes a 15 :a 14 10 0 1 $a000?$bfff lower 1/3 array: 8 kbytes a 15 :a 9 {1,a 14 :a 9 } 10 {1, a 14 :a 9 , 000000000} to {1, a 14 :a 9 , 111111111} eight rows: 512 bytes a 15 :a 6 {1,a 14 :a 6 } 11 {1, a 14 :a 6 , 000000} to {1, a 14 :a 6 , 111111} single row: 64 bytes advance information mc68hc908tv24 ? rev. 2.1 178 user flash memory freescale semiconductor user flash memory 12.7 flash program/margin read operation note: after a total of eight program operations have been applied to a row, the row must be erased bef ore further programming to avoid program disturb. an erased byte will read $00. programming of the user flash memory is do ne on a page basis. a page consists of eight consecutive bytes starting from address $xxx0 or $xxx8. the smart programming algo rithm is required to program every page in the flash memory. the smart programming algorithm is defined as an iterative program and margin read s equence. every page programming pulse (t step duration) is followed by a margin read. a margin read imposes a more stri ngent read condition on the bitcell than an ordinary read. as part of the margin read, a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower bitcell current. du ring these eight stretc h cycles, the cop counter continues to run. the user must ac count for these extra cycles within cop feed loops. the steps of programming and margin reading repeats until the data being programmed is identical to t he margin read data . this iterative process will ensure t hat data has been programm ed with sufficient margin for long-term dat a retention. note that a margin read operation can only follow a page pr ogramming operation. note: to overwrite a memory location, it must first be erased to 0s then programmed to the new value. for inst ance, if a location previously has been programmed to $aa (1010 1010 binary) and t he value should be changed to $55 (0101 0101 bi nary), it is necessary to erase $aa to $00 first before programming to $55. if the er ase operation in this example is not performed and $aa is simply re-programmed to $55, then the location will be r ead as $ff (1111 1111 binary). (0s cannot be programmed. 0s only result from the erase operation.) the smart programming algorithm cons ists of these steps. a flowchart for the algorith m is shown in figure 12-2 . values for the time parameters are specified in 25.11 memory characteristics . 1. set the pgm bit in fl1cr. this configures the memory for program operation and enables the latching of address and data for programming. user flash memory flash program/margin read operation mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 179 2. ensure that the block to be pr ogrammed is not pr otected by the settings in the fl1bpr register. re ad the fl1bpr register. if test voltage, v tst , is applied to the irq pin, block protection is bypassed. this bypass is useful when the entire array (including the fl1bpr regi ster) need to be altered. see 12.9 user flash block protect register . 3. write data to the eight bytes of the page being programmed. this requires eight separat e write operations. 4. set the hven bit. 5. wait for a time, t step . 6. clear the hven bit. 7. wait for a time, t hvtv . 8. set the margin bit. 9. wait for a time, t vtp . 10. clear the pgm bit. 11. wait for a time, t hvd . 12. read the eight data loca tions written in step 3 . this is a margin read. each read oper ation is stretched by eight cycles. 13. clear the margin bit. if margin read data is identical to write data t hen programming is complete. if this verify step fails, repea t from step 2 . note: while these operations mu st be performed in th e order shown, other unrelated operations may o ccur between the steps. this algorithm, which shoul d be repeated for all da ta to be programmed, guarantees the minimum po ssible program time and avoids the program disturb effect. note: to ensure proper flash r ead operation after comp letion of the smart programming algorithm, a series of 500 flash dummy reads must be performed of any address before accura te data is read from the flash. advance information mc68hc908tv24 ? rev. 2.1 180 user flash memory freescale semiconductor user flash memory figure 12-2. smart program ming algorithm flowchart program flash start initialize attempt set pgm bit and fdiv bits wait t hvtv wait t vtp set hven bit clear pgm bit set margin bit wait t hvd increment attempt counter y n counter to 0 y n programming operation failed programming operation complete write data to selected page wait t step clear hven bit margin read page of data clear margin bit margin read data equal to write data? attempt count equal to fls pulses ? read flash block note: this page program algorithm assumes the page to be programmed is initially erased. note: this algorithm is mandatory for programming the flash. protect register user flash memory user flash block protection mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 181 12.8 user flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by reserving a location in the memory for block protect information and requiring that this location be read to enable setting of t he hven bit. when the bl ock protect register is read, its contents are latched by the flash control logic. if the address range for an erase or progra m operation includ es a protected block, the pgm or eras e bit is cleared which pr events the hven bit in the flash control regist er from being set so t hat no high voltage is allowed in the array. note: in performing a program or erase op eration, the flash block protect register must be read after setting the pg m or erase bit and before asserting the hven bit. when the block protect regi ster is erased (all 0s), the entire memory is accessible for program an d erase. when bits wit hin the register are programmed, they lock blocks of memory address ranges as shown in 12.9 user flash block protect register . the presence of a voltage v tst on the irq pin will bypass the block prot ection so that all of the memory, including the block protec t register, is open for program and erase operations. be aware that a v tst voltage on irq when coming out of reset may force entry into monitor mode. see 16.4.1 entering monitor mode . advance information mc68hc908tv24 ? rev. 2.1 182 user flash memory freescale semiconductor user flash memory 12.9 user flash block protect register the block protect register (fl1bpr) is implemented as a byte within the user flash memory. each bit, when programmed, protects a range of addresses in the user flash. bpr3 ? block protec t register bit 3 this bit protects the memory cont ents in the addre ss range $f000 to $ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr2 ? block protec t register bit 2 this bit protects the memory cont ents in the address range $e000 to $ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr1 ? block protec t register bit 1 this bit protects the memory contents in t he address range $c000 to $ffff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr0 ? block protec t register bit 0 this bit protects the entir e array ($a000 to $ffff). 1 = address range protect ed from erase or program 0 = address range open to erase or program address: $ff80 bit 7654321bit 0 read: rrrrbpr3bpr2bpr1bpr0 write: reset:uuuuuuuu r = reserved u = unaffected by reset. initial value from factory is 0. figure 12-3. user flash block protect register (fl1bpr) user flash memory wait mode mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor user flash memory 183 by programming the block protect bi ts, a portion of th e memory will be locked so that no further eras e or program operations may be performed. programming more than one bit at a time is redundant. if both bpr3 and bp r2 are set, for instance, the address range $e000 through $ffff is locked. if all bits are erased, t hen all of the memory is available for erase and program. the pres ence of a voltage v tst on the irq pin will bypass the block protection so that all of the memory, including the block protect regist er, is open for program and erase operations. 12.10 wait mode putting the mcu into wa it mode while the flash is in read mode does not affect the operation of the flash me mory directly, bu t there will not be any memory activity si nce the cpu is inactive. the wait instruction should not be executed while performing a program or erase operat ion on the flash. when the mcu is put into wait mode, the charge pump for the fla sh is disabled so that either a program or erase operation will not continue. if t he memory is in either program mode (pgm = 1, hven = 1) or er ase mode (erase = 1, hven = 1), then it will remain in that mode during wait. exit from wait must now be done with a re set rather than an interr upt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. 12.11 stop mode when the mcu is put into stop mode, if the flash is in read mode, it will be put into low-power standby. ex it from stop is possible with an external interrupt, such as irq , keyboard interrupt, or reset. the stop instruction should not be executed while performing a program or erase operat ion on the flash. when the mcu is put into stop mode, the charge pump for the flash is disa bled so that either a program or erase operation will not continue. if t he memory is in either program mode (pgm = 1, hven = 1) or er ase mode (erase = 1, advance information mc68hc908tv24 ? rev. 2.1 184 user flash memory freescale semiconductor user flash memory heven = 1), then it will remain in that mode during stop. in this case, exit from stop must be done with a rese t rather than an interrupt because if exiting stop with an inte rrupt, the memory will not be in read mode and the interrupt vect or cannot be read from the memory. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display (osd) flash memory 185 advance information ? mc68hc908tv24 section 13. on-screen display (osd) flash memory 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 13.4 osd flash control register . . . . . . . . . . . . . . . . . . . . . . . . 187 13.5 charge pump frequency c ontrol . . . . . . . . . . . . . . . . . . . . . . 189 13.6 flash erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 13.7 flash program/margin r ead operation . . . . . . . . . . . . . . . . 192 13.8 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.9 osd flash block protect register. . . . . . . . . . . . . . . . . . . .193 13.2 introduction this section describes the operation of the embedded osd flash memory. this memory is used to store the pixel matrices of closed-caption and on-screen display (osd) characters. it can be read, programmed, and erased from a singl e external supply. the program, erase, and read operations are enabled through the use of an internal charge pump. advance information mc68hc908tv24 ? rev. 2.1 186 on-screen display (osd) flash memory freescale semiconductor on-screen display (osd) flash memory 13.3 functional description the osd flash memory is an array of 8,192 bytes used to store pixel matrices of closed-capt ion and osd characters. unlike the user flash, this memory is not connect ed directly to the inter nal bus. it is connected both to the osd module and to the internal bus through a set of multiplexers as shown in figure 13-1 . during normal operation, the memory is always connec ted to the osd module for read-only access. the cpu can take control of the memory for progr amming, erasing, and reading just by select ing addresses in the memory map space reserved for the osd fla sh ($8000?$9fff). figure 13-1. connection of the osd flash memory note: during normal operation the cpu should never try to access any address in the range $8000?$9fff. if this happens, the osd flash will be disconnected from the osd module and the television image will be corrupted. since the array sizes ar e different, the osd fla sh has a different page organization than the user flash. there are also eight pages of memory per row but only four byte s per page. the mini mum erase block size is a single row, 32 bytes. programming is performed on a per page osd flash data bus address bus & control internal address & data bus data bus address bus & control on-screen display (osd) flash memory osd flash control register mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display (osd) flash memory 187 basis; four bytes at a time.the address range for cpu access is $8000?$9fff. the same erasing and programming procedures outlined for the user flash in 12.3 functional description , 12.6 flash erase operation , and 12.7 flash program/margin read operation must be applied to the osd flash. although the osd flash is capable of storing 8, 192 bytes, the actual memory space required by the o sd module is only 6,528 bytes, occupying the range $8000?$9980. note: this flash does not ha ve security enabled. neve rtheless, it is still necessary to bypass security in or der to write onto it. this is true because the block protect register (fl2bpr) is on the user flash, which is protected by security. 13.4 osd flash control register the osd flash control register c ontrols flash program, erase, and verify operations. note: this register is not connec ted directly to the internal bus. it is connected to the same bus as t he osd flash and thus can only be accessed if the osd module is disa bled (osden = 0 in t he osd enable control register). fdiv1 ? frequency di vide control bit this read/write bit togethe r with fdiv0 selects th e factor by which the charge pump clock is divided from the system clock. see 13.5 charge pump frequency control . address: $fe09 bit 7654321bit 0 read: fdiv1 fdiv0 blk1 blk0 hven margin erase pgm write: reset:00000000 figure 13-2. flash cont rol register (fl2cr) advance information mc68hc908tv24 ? rev. 2.1 188 on-screen display (osd) flash memory freescale semiconductor on-screen display (osd) flash memory fdiv0 ? frequency di vide control bit this read/write bit togethe r with fdiv1 selects th e factor by which the charge pump clock is divided from the system clock. see 13.5 charge pump frequency control . blk1? block erase control bit this read/write bit together with blk0 allows erasing of blocks of varying size. see 13.6 flash erase operation for a description of available block sizes. blk0 ? block erase control bit this read/write bit together with blk1 allows erasing of blocks of varying size. see 13.6 flash erase operation for a description of available block sizes. hven ? high-volt age enable bit this read/write bit enables high vo ltage from the charge pump to the memory for either progra m or erase operation. it can only be set if either pgm or erase is high and the s equence for erase or program/margin read is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off margin ? margin read control bit this read/write bit confi gures the memory for ma rgin read operation. it cannot be set if the hven bit is high, and if it is high when hven is set, it will automatically return to 0. 1 = margin read operation selected 0 = margin read oper ation unselected erase ? erase control bit this read/write bit configures the memory fo r erase operation. it is interlocked with the pgm bit such t hat both bits ca nnot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected on-screen display (osd) flash memory charge pump frequency control mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display (osd) flash memory 189 pgm ? program control bit this read/write bit config ures the memory for pr ogram operation. it is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 13.5 charge pump frequency control the internal charge pump is designed to operate at greatest efficiency with an internal frequen cy of about 2 mhz. table 13-1 shows how the fdiv bits are used to select a charge pump frequency and the recommended bus frequency ranges for each confi guration. program and erase operations can not be performed if th e pump clock frequency is below 2 mhz. note: since only one charge pump circui t services both flash arrays, the actual fdiv bits receiv ed by the charge pump is the logical or of the individual fdiv bits of registers fl1cr and fl2cr. table 13-1. charge pump clock frequency fdiv1 fdiv0 pump clock frequency bus frequency 0 0 bus frequency 1 2 mhz 10% 0 1 bus frequency 2 4 mhz 10% 1 0 bus frequency 2 4 mhz 10% 1 1 bus frequency 4 8 mhz 10% advance information mc68hc908tv24 ? rev. 2.1 190 on-screen display (osd) flash memory freescale semiconductor on-screen display (osd) flash memory 13.6 flash erase operation use the following procedure to erase a block of flash memory (to read as logic 0). values for the ti me parameters ar e specified in 25.11 memory characteristics . 1. set the erase bit, the blk0, blk1, fdiv0, and fdiv1 bits in fl2cr. see table 13-1 for fdiv settings. see table 13-2 for block sizes. 2. ensure that the block to be erased is not protected by the settings in the fl2bpr register. read t he fl2bpr regist er ($ff81) which is physically located on the ot her flash. if te st voltage, v tst , is applied to the irq pin, block protection is bypassed. see 13.9 osd flash block protect register . 3. write to any flash address wi th any data within the block address range desi red. if address is in a protected area, the erase bit will be clear ed and the following st eps of the erase procedure are blocked. 4. set the hven bit. 5. wait for a time, t erase . 6. clear the hven bit. 7. wait for a time, t kill , for the high volt ages to dissipate. 8. clear the erase bit. 9. after a time, t hvd , the memory can be accessed in read mode again. note: while these operations mu st be performed in th e order shown, other unrelated operations may occur betw een the steps. do not exceed t erase maximum. table 13-2 shows the various block si zes which can be erased in one erase operation. on-screen display (osd) flash memory flash erase operation mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display (osd) flash memory 191 in step 3 of the eras e operation, the desired erase addresses are latched and used to determine the lo cation of the block to be erased. for the full array (blk1 = 0, blk0 = 0), the only requirement is that the flash memory be selected. wr iting to any address in the range $8000 to $9fff will enabl e the full array erase. in the ?upper 1/2 arra y? case (blk1 = 0, bl k0 = 1), the state of a 15 :a 12 = 1001 determines that the r ange from $9000 to $9fff is erased. for example, writing to address $9123 will erase the range $9000 to $9fff. in the ?lower 1/2 arra y? case (blk1 = 0, bl k0 = 1) the state of a 15 :a 12 = 1000 determines that the r ange from $8000 to $8fff is erased. for example, writing to address $8623 will erase the range $8000 to $8fff. in the ?eight row? erase operation (blk1 = 1, blk0 = 0), 256-byte blocks are erased as determined by upper addresses a 15 :a 8 . for example, writing to address $8b10 will erase the range $8b00 to $8bff. in the ?single row? eras e operation (blk1 = 1, bl k0 = 1), 32-byte blocks are erased as determined by upper addresses a 15 :a 5 . for example, writing to address $9c60 will erase the range $9c60 to $9c7f. table 13-2. erase block sizes write to address bits address value blk1 blk0 desired erase address array array size any flash addr any 0 0 $8000?$9fff full array: 8,192 bytes a 15 :a 12 1001 0 1 $9000?$9fff ?upper 1/2? array: 4,096 bytes a 15 :a 12 1000 0 1 $8000?$8fff ?lower 1/2? array: 4,096 bytes a 15 :a 8 {100, a 12 :a 8 } 10 {100, a 12 :a 8 , 00000000} to {100, a 12 :a 8 , 11111111} eight rows: 256 bytes a 15 :a 5 {100, a 12 :a 5 } 11 {100, a 12 :a 5 , 00000} to {100, a 12 :a 5 , 11111} single row: 32 bytes advance information mc68hc908tv24 ? rev. 2.1 192 on-screen display (osd) flash memory freescale semiconductor on-screen display (osd) flash memory 13.7 flash program/margin read operation programming of the os d flash memory is done using the same procedures outlined in 12.7 flash program/margin read operation . the main difference here is that a page consists of only four consecutive bytes instead of eight. a 4-byte page st arts at the addr ess {a15:a3,000} or {a15:a3,100}. the smart programming algori thm applied to this flash consists of the following steps: 1. set the pgm bit in fl2cr. this configures the memory for program operation and enables the latching of address and data for programming. 2. ensure that the block to be pr ogrammed is not pr otected by the settings in the fl2bpr register. read the fl2bpr register, which is physically located on the ot her flash. if te st voltage, v tst , is applied to the irq pin, block protection is bypassed. see 13.9 osd flash block protect register . 3. write data to the four bytes of the page being programmed. this requires four separat e write operations. 4. set the hven bit. 5. wait for a time, t step . 6. clear the hven bit. 7. wait for a time, t hvtv . 8. set the margin bit. 9. wait for a time, t vtp . 10. clear the pgm bit. 11. wait for a time, t hvd . 12. read the four data locations writ ten in step 3. this is a margin read. each read oper ation is stretched by eight cycles. 13. clear the margin bit. if margin read data is identical to write dat a, then programming is complete. if this verify step fails, repea t from step 2. on-screen display (osd) flash memory block protection mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display (osd) flash memory 193 13.8 block protection the osd flash has the same block pr otection mechanism as the user flash. the difference is that the block pr otect register is not one of the memory positions of the osd flash. instead, it is physically located on the other flash memo ry, at location $ff81. when the block protect regi ster is erased (all 0s), the entire memory is accessible for program an d erase. when bits wit hin the register are programmed, they lock blocks of me mory address ranges as discussed in 13.9 osd flash blo ck protect register . the presence of a voltage v tst on the irq pin will bypass the block prot ection mechanism so that all of the memory is open for progr am and erase operat ions. be aware that a v tst voltage on irq when coming out of rese t may force entry into monitor mode. see 16.4.1 entering monitor mode . 13.9 osd flash block protect register the block protect register is implem ented as a byte wi thin the user flash memory. since the regist er is implemented in flash, upon reset the bits will come up in the st ate that was last defined by the user. each bit, when programmed, protec ts a range of addresses in the osd flash. address: $ff81 bit 7654321bit 0 read: rrrrbpr3bpr2bpr1bpr0 write: reset: unaffected by reset r= reserved figure 13-3. osd flash block protect register (fl2bpr) advance information mc68hc908tv24 ? rev. 2.1 194 on-screen display (osd) flash memory freescale semiconductor on-screen display (osd) flash memory bpr3 ? block protec t register bit 3 this bit protects the memory contents in t he address range $9c00 to $9fff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr2 ? block protec t register bit 2 this bit protects the memory conten ts in the addres s range $9800 to $9fff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr1 ? block protec t register bit 1 this bit protects the memory conten ts in the addres s range $9000 to $9fff. 1 = address range protect ed from erase or program 0 = address range open to erase or program bpr0 ? block protec t register bit 0 this bit protects the entir e array ($8000 to $9fff). 1 = address range protect ed from erase or program 0 = address range open to erase or program by programming the block protect bi ts, a portion of th e memory will be locked so that no further eras e or program operations may be performed. programming more than one bit at a time is redundant. if both bit 3 and bit 2 are set, fo r instance, the address range $9800 through $9fff is locked. if all bits ar e erased, then all of the memory is available for erase and progra m. the presence of a voltage v tst will bypass the block protection so that a ll of the memory, including the block protect register, is open for program and eras e operations. note: since the block protect register is located physically in the flash array occupying the address range $a000?$ffff, the user must ensure that the block protect bits in fl1bpr do not prevent the programming of fl2bpr. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor external interrupt (irq) 195 advance information ? mc68hc908tv24 section 14. external interrupt (irq) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 14.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 199 14.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 199 14.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 14.3 features features of the irq module include: a dedicated external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge advance information mc68hc908tv24 ? rev. 2.1 196 external interrupt (irq) freescale semiconductor external interrupt (irq) 14.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 14-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears t he latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate ackn owledge bit in the in terrupt status and control register (intscr). writing a logic 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software-configurable to be eit her falling-edge or falling-edge and low-level-triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, softwa re clear, or reset occurs. when an interrupt pin is both falli ng-edge and low-level-triggered, the interrupt remains set until both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bit in the intscr mask a ll external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. external interrupt (irq) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor external interrupt (irq) 197 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external interrupt requests. figure 14-1. irq module block diagram irq ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset addr.register name bit 7654321bit 0 $0007 irq status and control register (intscr) see page 199. read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 14-2. irq i/o register summary advance information mc68hc908tv24 ? rev. 2.1 198 external interrupt (irq) freescale semiconductor external interrupt (irq) 14.5 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falli ng-edge-sensitive and low-level-sensitive. with mode set, both of the follow ing actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the interrupt stat us and control register (intscr). the ack bit is useful in appl ications that poll the irq pin and require software to clear the irq la tch. writing to the ack bit prior to leaving an interrupt service r outine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge occurs after writing another interrupt request to the ack bit. if the irq mask bit, imask, is clear, t he cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the return of the irq pin to logic 1 may occur in any order. the inte rrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq pin. external interrupt (irq) irq module during break interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor external interrupt (irq) 199 note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. 14.6 irq module during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. see section 6. break module (brk) . to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect cpu interrupt fl ags during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), writing to the ack bit in the irq status and control regi ster during the br eak state has no effect on the ir q interrupt flags. 14.7 irq status and control register the irq status and control register (intscr) controls and monitors operation of the irq module. the intscr: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq interrupt pin advance information mc68hc908tv24 ? rev. 2.1 200 external interrupt (irq) freescale semiconductor external interrupt (irq) irqf ? irq flag bit this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt re quest acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on fa lling edges and low levels 0 = irq interrupt requests on falling edges only address: $0007 bit 7654321bit 0 read: irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 14-3. irq status and control register (intscr) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-voltage inhibit (lvi) 201 advance information ? mc68hc908tv24 section 15. low-voltage inhibit (lvi) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 15.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .204 15.4.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . 204 15.4.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.5 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 15.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 15.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 15.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 15.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 15.2 introduction this section describes the low-vo ltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lv i trip falli ng voltage, v tripf . advance information mc68hc908tv24 ? rev. 2.1 202 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 15.3 features features of the lvi module include: programmable lvi reset selectable lvi trip voltage programmable st op mode operation 15.4 functional description figure 15-1 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module cont ains a bandgap reference circuit and comparator. clearing t he lvi power disable bi t, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi re set disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable bit (lvistop) in stop mode bit enables the lvi to operate in stop m ode. setting the lvi 5-v or 3-v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. cleari ng the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip points are shown in section 25. preliminary electrical specifications . note: after a power-on reset (por) the lvi? s default mode of operation is 3 v. if a 5-v system is used, the user must set the lv i5or3 bit to raise the trip point to 5- v operation. note that this must be done after every power-on reset since the default will revert back to 3-v mode after each power-on reset. if the v dd supply is below the 5- v mode trip voltage but above the 3-v mode trip voltage when por is releas ed, the part will operate because v tripf defaults to 3-v mode af ter a por. so, in a 5-v system care must be tak en to ensure that v dd is above the 5-v mode trip voltage afte r por is released. note: if the user requires 5- v mode and sets the lvi5 or3 bit after a power-on reset while the v dd supply is not above the v tripr for 5-v mode, the mcu will immediately go into reset. the lvi in this case will hold the part in reset until either v dd goes above the risi ng 5-v trip point, v tripr , which will release reset or v dd decreases to approxima tely 0 v which will re-trigger the power-on re set and reset the trip point to 3- v operation. low-voltage inhibit (lvi) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-voltage inhibit (lvi) 203 lvistop, lvipwrd, lv i5or3, and lvirstd are in the configuration register (config). see 9.3 functional description for details of the lvi?s configuration bits. once an lv i reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 20.4.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of t he lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 15-1. lvi m odule block diagram low v dd detector lv i p w r d stop instruction lv i s to p lvi reset lv i o u t v dd > lvi trip = 0 v dd lvi trip = 1 from config from config v dd from config lv i r s t d lv i 5 o r 3 from config addr.register name bit 7654321bit 0 $fe0f lvi status register (lvisr) see page 205. read: lviout 0000000 write: reset:00000000 = unimplemented figure 15-2. lvi i /o register summary advance information mc68hc908tv24 ? rev. 2.1 204 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 15.4.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bi t. in the configuration register, the lvipwrd bi t must be at logic 0 to enable the lvi module, and the lvirstd bi t must be at logic 1 to disable lvi resets. 15.4.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi reset allows the lvi m odule to reset the mcu when v dd falls below the v tripf level. in the configurat ion register, the lvipwrd and lvirstd bits must be at logic 0 to enable the lv i module and to enable lvi resets. 15.4.3 voltage hysteresis protection once the lvi has triggered by having v dd fall below v tripf , the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 15.4.4 lvi trip selection the lvi5or3 bit in the conf iguration register sele cts whether the lvi is configured for 5-v or 3-v protection. note: although the lvi can be configured for 3 v protection, the microcontroller itself may or may not have been designed to operate with 3 v supply voltage. see section 25. preliminary electrical specifications for minimum supply and lvi trip point voltages.) low-voltage inhibit (lvi) lvi status register mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor low-voltage inhibit (lvi) 205 15.5 lvi status register the lvi status register (l visr) indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag be comes set when the v dd voltage falls below the v tripf trip voltage. (see table 15-1 .) reset clears the lviout bit. 15.6 lvi interrupts the lvi module does not gener ate interrupt requests. address: $fe0f bit 7654321bit 0 read: lviout 0000000 write: reset:00000000 = unimplemented figure 15-3. lvi stat us register (lvisr) table 15-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value advance information mc68hc908tv24 ? rev. 2.1 206 low-voltage inhibit (lvi) freescale semiconductor low-voltage inhibit (lvi) 15.7 low-power modes the stop and wait instructi ons put the mcu in low power-consumption standby modes. 15.7.1 wait mode if enabled, the lvi module remains acti ve in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 15.7.2 stop mode if enabled in stop mode (l vistop set), the lvi module remains active in stop mode. if enabled to gener ate resets, the lvi module can generate a reset and bring t he mcu out of stop mode. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 207 advance information ? mc68hc908tv24 section 16. monitor rom (mon) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 16.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 16.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.4.6 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.2 introduction this section describes the moni tor rom (mon). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. advance information mc68hc908tv24 ? rev. 2.1 208 monitor rom (mon) freescale semiconductor monitor rom (mon) 16.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 16.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 16-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute c ode download into ram by a host computer while most mcu pins reta in normal operating mode functions. all communication between the host computer and t he mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and require s a pullup resistor. the mc68hc908tv24 has a flash security feature to prevent external viewing of the contents of flash. proper procedures must be followed to verify flash content. access to the flash is denied to unauthorized users of customer specified software (see 16.4.6 security ). monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 209 figure 16-1. moni tor mode circuit + + + v dd v tst mc145407 mc74hc125 68hc08 rst irq cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 0.1 f 10 ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 10 k ? ptc3 v dd 10 k ? b a note: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 + ptc0 ptc1 v dd 10 k ? v ssosd v ddcgm v dda v ddosd v sscgm v dd f ext pta7 advance information mc68hc908tv24 ? rev. 2.1 210 monitor rom (mon) freescale semiconductor monitor rom (mon) 16.4.1 entering monitor mode table 16-1 shows the pin conditions for entering monitor mode. cgmout/2 is the internal bus cl ock frequency. if ptc3 is low upon monitor mode entry, cgmout is equ al to the frequency of cgmxclk, which is a buffered vers ion of the clock on t he osc1 pin. the bus frequency in this case is a divide-by-t wo of the input clock. if ptc3 is high upon monitor mode entry, t he bus frequency will be a divide-by-four of the input clock if the pll is not engaged. the pll can be engaged to multiply the bus frequency by programming the cgm. refer to section 7. clock generator module (cgmc) for information on how to program the pll. when t he pll is used, ptc3 must be logic 1 during monitor mode entry, and the bus frequency will be a divide-by-four of cgmvclk, the output clock of the pll. note: holding the ptc3 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage in the oscillator. in this case, the cgmout frequency is equal to the cgmxclk (external clock) frequency. the osc1 signal must ha ve a 50 percent duty cycle at maximum bus frequency. enter monitor mode with the pi n configuration shown in table 16-1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. table 16-1. mode selection irq pin pta7 pin pta0 pin ptc3 pin ptc0 pin ptc1 pin mode cgmout bus frequency v tst (1) 0 1 1 1 0 monitor or v tst (1) 0 1 0 1 0 monitor cgmxclk 1. for v tst , see 25.6 5.0-v dc electrical characteristics . cgmxclk 2 ------------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 211 note: the pta7 pin must remain at logi c 0 for 24 bus cycles after the rst pin goes high. once out of reset, the mcu waits for the host to send eight security bytes (see 16.4.6 security ). after the security byte s, the mcu sends a break signal (10 consecutive logi c 0s) to the host computer, indicating that it is ready to receive a command. the break signal also serv es as a timing reference to allow t he host to determine t he necessary baud rate monitor mode uses alter nate vectors for reset, swi, and break interrupt to those used in user mode. the alter nate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. when the host computer has comple ted downloading code into the mcu ram, this code can be ex ecuted by driving pta0 low while asserting rst low and then high. the in ternal monitor rom fi rmware will interpret the low on pta0 as an i ndication to jump ram, and execution control will then continue from ram. the location jumped to is always the second byte of ram (for exampl e, the first ram byte add ress + 1). execution of an swi from the dow nloaded code will return program control to the internal monitor rom firmware. alt ernatively, the host can send a run command, which executes an rti, and this can be used to send control to the address on t he stack pointer. the cop module is disabled in monitor mode as long as v tst is applied to either the irq pin or t he reset pin. advance information mc68hc908tv24 ? rev. 2.1 212 monitor rom (mon) freescale semiconductor monitor rom (mon) table 16-2 is a summary of the differ ences between user mode and monitor mode. 16.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. trans mit and receive baud rates must be identical. see figure 16-2 and figure 16-3 . figure 16-2. moni tor data format figure 16-3. sample monitor waveforms table 16-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v tst ) is removed from the irq pin or the rst pin while in monitor mode, the sim asserts its cop enable out put. the cop is mask option enabled or dis- abled by the copd bit in the configuration register. $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 213 16.4.3 break signal a start bit followed by nine low bits is a break signal. see figure 16-4 . when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 16-4. break transaction 16.4.4 baud rate the bus clock frequency for the mcu in monitor mode is determined by the external clock frequency, the value on ptc3 during monitor mode entry, and whether or not the pll is engaged. the internal monitor firmware performs a divi sion by 256 (for sampli ng data). therefore, the bus frequency divided by 2 56 is the baud rate of the monitor mode data transfer. for example, with a 4.9152-mhz exter nal clock and the pt c3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. the internal pll can be engaged to incr ease the baud rate of instruction transfer between the host and the mcu and to increase the speed of program execution. refer to section 7. clock generator module (cgmc) for information on how to program the pll. if use of the pll is desired, the monitor mode must be entered with ptc high. see 16.4.1 entering monitor mode . initially, the bus frequ ency is a divide-by-four of the input clock. after the pll is programm ed and enabled onto the bus, communication be tween the host and mcu must be re-established 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo advance information mc68hc908tv24 ? rev. 2.1 214 monitor rom (mon) freescale semiconductor monitor rom (mon) at the new baud rate. one way of accomplishing this would be for the host to download a program into th e mcu ram that w ould program the pll and send a new baud rate flag to t he host just prior to engaging the pll onto the bus. upon completion of execution, an swi would return program control to t he monitor firmware. 16.4.5 commands the monitor rom uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program as the host computer sends commands through pta0, the monitor rom firmware immediately echoes each re ceived byte back to the pta0 pin for error checking, as show n in the example command in figure 16-5 . figure 16-5. re ad transaction the resultant data of a read type of command appears after the echo of the last byte of the command. a brief description of each monitor mode command follows. a sequence of iread or iwrite co mmands can access a block of memory sequentially over th e full 64-kbyte memory map. addr. high opcode opcode addr. high addr. low addr. low data echo sent to monitor result monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 215 figure 16-6. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result figure 16-7. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data advance information mc68hc908tv24 ? rev. 2.1 216 monitor rom (mon) freescale semiconductor monitor rom (mon) figure 16-8. iread (indexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result figure 16-9. iwrite (i ndexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 217 figure 16-10. reads p (read stack po inter) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result figure 16-11. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor advance information mc68hc908tv24 ? rev. 2.1 218 monitor rom (mon) freescale semiconductor monitor rom (mon) 16.4.6 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. lo cations $fff6?$fffd contain user-defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pa0. figure 16-12. moni tor mode entry timing if the received bytes match thos e at locations $fff6?$fffd, the host bypasses the security feature an d can read all fla sh locations and execute code from flash . security remains by passed until a power-on reset occurs. after the host bypasses security, any reset other than a byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 pa7 rst v dd 4096 + 32 cgmxclk cycles 24 cgmxclk cycles 256 cgmxclk cycles (one bit time) 1 4 1 1 2 1 break note: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 4 = wait 1 bit time before sending next byte. 4 from host from mcu monitor rom (mon) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor monitor rom (mon) 219 power-on reset requires the host to se nd another eight bytes. if the reset was not a power-on reset, the securi ty remains bypassed regardless of the data that the host sends. if the received bytes do not ma tch the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading flash locations returns undefined data, and trying to execute code from flash causes an illegal add ress reset. after the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. after receiving the eight security by tes from the host, the mcu transmits a break character signa lling that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bytes. advance information mc68hc908tv24 ? rev. 2.1 220 monitor rom (mon) freescale semiconductor monitor rom (mon) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 221 advance information ? mc68hc908tv24 section 17. on-screen display module (osd) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 17.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 17.4.1 single-row architecture . . . . . . . . . . . . . . . . . . . . . . . . . . .225 17.4.2 display timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 17.4.3 registers and pixel memo ry . . . . . . . . . . . . . . . . . . . . . . .226 17.4.4 osd output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.5 display characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.1 closed-caption mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 17.5.2 on-screen display mode . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.6 flash programming guideli nes . . . . . . . . . . . . . . . . . . . . . . 234 17.7 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.7.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.7.2 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.7.3 software controlled feat ures. . . . . . . . . . . . . . . . . . . . . . . 242 17.8 input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.8.1 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.2 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.3 pll filter pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.8.4 output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.9 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 17.9.1 osd character registers. . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.9.2 osd vertical delay r egister . . . . . . . . . . . . . . . . . . . . . . .251 17.9.3 osd horizontal delay register . . . . . . . . . . . . . . . . . . . . . 252 17.9.4 osd foreground control register . . . . . . . . . . . . . . . . . . . 252 17.9.5 osd background control register . . . . . . . . . . . . . . . . . . 254 17.9.6 osd border control re gister. . . . . . . . . . . . . . . . . . . . . . . 255 17.9.7 osd enable control register . . . . . . . . . . . . . . . . . . . . . . 257 advance information mc68hc908tv24 ? rev. 2.1 222 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.9.8 osd event line register . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.9.9 osd event count regist er . . . . . . . . . . . . . . . . . . . . . . . . 260 17.9.10 osd output control re gister. . . . . . . . . . . . . . . . . . . . . . . 260 17.9.11 osd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 17.9.12 osd matrix start regist er . . . . . . . . . . . . . . . . . . . . . . . . . 263 17.9.13 osd matrix end regist er . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 17.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 17.11 interrupts and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 17.2 introduction the on-screen display (osd ) module converts programmed character addresses and control information in to digital color, intensity, and blanking outputs to disp lay user-defined charac ters on a television screen for on-screen programmi ng and closed-c aption (cc) applications. 17.3 features the osd module provi des these features: 192 user-defined (program mable in flash memory) 9 x 13 characters for use in cc mode 126 user-defined (program mable in flash memory) 12 x 18 characters for use in osd mode 34 columns by 16 rows in cc mode (standard size) 24 columns by 12 rows in osd mode (standard size) on-screen display module (osd) features mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 223 software selectable character attributes: ? 16 foreground colors (8 colo rs and 2 intensity levels) ? 16 background colors ? 16 border colors (area outsi de foreground and background) ? rounding ? black outline ? 3d shadow (osd mode only) ? underline and italics (in cc mode only) in osd mode, two for eground colors are poss ible in one character with the use of backspace ov erlaying of two characters closed-caption characte rs are fixed size, but osd characters may have three different sizes, sele ctable on a row-by-row basis: (1w x 1v), (1.5w x 2v), and (2w x 2v) programmable horizontal and vertical positioning software controlled features: ? soft scrolling ?blinking programmable polarity of r, g, b, i, and fbkg zero inter-column and inter-row sp acing, so composed characters can be formed by abutment advance information mc68hc908tv24 ? rev. 2.1 224 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.4 overview the osd uses single character row arch itecture instead of a full-screen display ram in order to mini mize die area and address space requirements. figure 17-1 shows a block di agram of the osd. figure 17-1. osd block diagram hsync vsync pll dot & line counters r, g, b, i, fbkg attribute adder parallel-to-serial clock scan line counter vertical bit event line match display mode control char 1 char 2 ... char 34 rank 2 mcu internal bus event line register character rank 1 comp cc rom osd rom counter counter on-screen display module (osd) overview mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 225 17.4.1 single-row architecture the basic concept of single-row ar chitecture is to use one row of double-ranked registers to do the communicati on between the cpu and the display. the cpu writes the data of the next row to be displayed into the first rank of registers. it also writes the target line in which this row is to be displayed on the event line register. meanwhile, a counter (accessible through the ev ent register) keeps tra ck of the current line being displayed. this li ne counter is continuou sly compared to the contents of the event line register. when a match o ccurs, all the external rank is loaded into the internal r ank and an interrupt request (event line match interrupt) is optionally gene rated to notify the cpu of the availability of the external rank fo r the next row of characters to be displayed. for the display of one row only, the cp u can leave the registers unchanged all t he way. for two adjacent rows, the cpu must update the buffer within a period of a one-row di splay. in cc mode, this period is 63.5 x 13 = 825 s. 17.4.2 display timing the osd horizontal timing is based on an independent on-ch ip oscillator that is phase locked to the starting edge of the internal horizontal sync pulse. the osd vertical timing is syn chronized to the starting edge of the internal vertical sync pulse, so that stable display is possible with either 525 or 625 line systems. an interrup t is optionally generated at every starting edge of the vertical sync pul se. this interrupt can be used to determine which television system is being received: 60 hz (525 lines) or 50 hz (625 lines). kno wing which tv system is being received, the software must program the vertical delay regi ster and the horizontal delay register to best fi t the active display ar ea on the screen, as shown in figure 17-2 . the active display area o ccupies 16 rows by 34 columns in cc mode and 12 rows by 24 columns in osd mode. advance information mc68hc908tv24 ? rev. 2.1 226 on-screen display module (osd) freescale semiconductor on-screen display module (osd) figure 17-2. active display area 17.4.3 registers and pixel memory the majority of the osd register s are double-rank ed because the osd must read the values for the current row while the cpu writes the values for the next row. the external rank cons ists of a set of r egisters visible to the cpu, containi ng the character codes and control information relevant to a single ro w on the display screen. these registers appear in the register space and t heir bits are readable as well as writable. the internal rank is parallel shifted from the exter nal rank whenever the osd is ready to display the next row. th e internal rank feeds the character generation logic of the osd. character codes are read sequentially from the in ternal rank of the character registers during each sc an line. each code, along with the scan line number within the character ro w, is used as an address to fetch the pixel pattern from the cc rom (in cc mode) or from the osd rom (in osd mode). the cc rom contains 192 user-defined (programmable in flash memory) 9 x 13 pixel matrix characters used exclusively for closed-caption display. the osd rom contains another 128 user-definable (also programmable in flash memory) 12 x 18 pixel matrix characters used for o sd display. character codes may alternately be interpreted as control codes t hat alter display attributes in the middle of a row. active display area tv picture area horizontal delay register vertical delay register on-screen display module (osd) overview mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 227 17.4.4 osd output logic programmable character attribut es include color (foreground and background), rounding, bl ack outline, 3d shad ow (osd mode only), blinking, underlining and it alics (both in cc mo de only). rounding and outline dots are half t he width and length of th e basic rom character pixel. in the vertical dimension, ea ch pixel of the c haracter matrix is formed by a pair of odd and even lines of different interlace fields. to produce the half-pixel roundi ng dot, the spatial disp lacement of odd and even fields of the interlac ed video is used, so that just one of the fields displays the rounding or outline dot . the odd/even field indicator is extracted by the closed-caption data slicer, which must be enabled to provide field information to the osd. these attributes have a default set on a row basis, and many of them can be modified inside t he row by control char acters. the cc mode and the osd mode have differ ent character control codes and the display behavior is different for each mode. in cc mode, all mid-row control characters are displayed as backgr ound color spaces, whereas in osd mode, up to two control characters can be placed togethe r without being displayed. in osd mode it is also possible to backspace a character and display it on top of t he preceding one, allowing the use of more than one foreground color in one character. the pixel pattern data from the pixel rom passes through circuitry which adds the selected attributes of r ounding, black outli ne, shadow, italics and underline. the resultin g signal passes through a color encoder and is converted into r, g, b, i, and fbkg signals. in osd mode, if a backspace control code appears betwe en two characters, the second one is read at the same time as t he first, and the tw o of them go in parallel to the color encoder to form a composite character. in this case it is possible to apply rounding, black outline and shadow only to the first character. the second one is add ed with no attributes applied. advance information mc68hc908tv24 ? rev. 2.1 228 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.5 display characteristics two display modes affect the app earance and attributes of the characters on the screen: the cc mode and the osd mode. the display mode can be programmed for each row by writing into bit 7 of the matrix start register. 17.5.1 closed-caption mode in closed-caption mode, the character is defined on a 9 x 13 pixel matrix, as shown in figure 17-3 . attributes that can be added in this mode are rounding, black outline, underline and it alics. rounding dots, which are generated to smooth diagonals, are half the size of a normal rom pixel and are displayed in the foreground color. black-out line dots, also half the size of a normal rom pixel, are displaye d in black to outline a character and improve r eadability. the underline attribute will generate a line of pixels which are of the same color and size as the rom pixels. underline will affect all characters with the exce ption of the border space ($00), background space ($01 ), and control codes. the italics attribute does not generate any additional pixels, but will slant t he display of the character. figure 17-3. cc-rom pixel matrix basic rom pixel rounding dot black outline dot underline on-screen display module (osd) display characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 229 the background is the region of the ch aracter matrix where rom pixels are zero and there are no rounding, black outli ne or underline dots. background may be a solid color or tr ansparent, in which case the video will show through (regardless of border color selection). border is displayed wherever th ere is no foregr ound or background inside the active display area. bor der may also be a solid color or transparent. border can be specifi ed for a character within a row by using the border space characte r. when background or border are transparent, the video intensity can be specified to be half-tone to improve readability. the horizontal delay of the active display area from each hsync pulse is given by a minimum fixed delay of 14.1 s plus an additional delay specified on the horiz ontal delay register (32 increments of 0.14 s). this delay does not depend on the characte r size programmed for each row. the border space character can be us ed to provide further indentation in a row-by-row basis. vertical positioning of the active disp lay area is specifi ed in the vertical delay register. this delay is measured in lines from th e starting edge of the vertical sync pulse. ve rtical positioning inside the active display area is indicated by t he contents of the event line register. scrolling can be accomplished in soft ware by modifying the vertical positioning of a row, in conjunction with specif ying the subset of horizontal lines of the ro w to display. the matrix start register and the matrix end register indicate, respective ly, the first and last lines of a row to be displayed. all lines before and after the li nes displayed are filled in with border. boundaries between border and character display are always vertical. if italics are not enabled, the width of a border space character is the same as the width of a rom character. if italics are enabled, the boundaries of the border space characte r are not slanted, but the width occupied by this space is smaller than the width of a rom charac ter by five dots (see figure 17-4 ). advance information mc68hc908tv24 ? rev. 2.1 230 on-screen display module (osd) freescale semiconductor on-screen display module (osd) figure 17-4. boundary c onditions with italics 17.5.2 on-screen display mode in on-screen display mode, the character is de fined on a 12 x 18 pixel matrix, as shown in figure 17-5 . attributes that can be added in this mode are rounding, bla ck outline, blinking, shadow, not-pressed three-dimensional (3 d) shadow and presse d 3d-shadow. rounding, black outline, and blinking are iden tical as in cc mode. shadow is generated to simulate the effect of a light source situated in the northwest corner. the not-pressed 3d-s hadow simulates the effect of a 3d object by putting a white outline on the side near the light source, and a black outline on the opposite side. the pressed 3d -shadow does the contrary, putting a bla ck outline on the side near the light source, and a white outline on t he opposite side (see figure 17-6 ). background, border, horizontal delay , vertical delay , and scrolling behave the same as in cc mode and the sa me registers control them. the only exception is the appearance of the control characters. in cc mode they appear as backgr ound spaces. in osd mode it is possible to use up to two consecutive control char acters without any of them being displayed. this is shown in figure 17-7 . as a consequence, a single control character can not be used to add a space. one must use a border space ($00) or a background space ($ 01). if three consecutive control characters are used, a ba ckground space will be added. reduced border space on-screen display module (osd) display characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 231 figure 17-5. osd-ro m pixel matrix with northwest shadow figure 17-6. exam ple of 3d shadow advance information mc68hc908tv24 ? rev. 2.1 232 on-screen display module (osd) freescale semiconductor on-screen display module (osd) figure 17-7. behavior of control char acters in osd mode character size is determined in t he foreground contro l register. there are three possible sizes: 1w, 1.5w , and 2w, where w refers to the width. the height s of 1.5w and 2w are twice that of the 1w size. size is fixed for an entire row. the 1w-size character is 12 pixels in width and 18 scan lines in height . a maximum of 24 1w-characters may be displayed per row. the 1.5w-size char acter is 18 pixels in width and 36 scan lines in height a nd has a maximum of 16 c haracters per row. the 2w-size character is 24 pixels in width and 36 scan lines in height, and has a maximum of 12 characters per row. a unique feature t hat appears only in osd mode is the possibility of overlaying two characters to form a composite one. this is controlled by the backspace (bs) bit, which appears in format a of the character control code. this code must be put between two characters and must be the only one between t hem. its effect is to overlay the second character on top of the first one. figure 17-8 illustrates this feature. the way in which the foreground colors w ill be combined c an be specified in one of two forms: first, the second character will always win; second, the resulting foreground colo r will be the x-or of th e individual rgb bits. using this feature, it is possible to have up to three foreground colors, but there are some limita tions. it is not possible to add attributes to the second character. as a consequence, only the fi rst character can have rounding, black outline and shadow. the backgro und color of the composite character will be the backg round color of t he first character. abc de tv screen abctrctrc $01de row buffer on-screen display module (osd) display characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 233 figure 17-8. overlaying characters to get two for eground colors advance information mc68hc908tv24 ? rev. 2.1 234 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.6 flash programming guidelines the description presented here alwa ys refers to two separate rom memories storing pixe l information, one for closed-caption and one for on-screen display. alt hough this makes it easi er to understand the module behavior, the actual physica l implementation has only one programmable flash memory occupy ing the mcu memory space in the address range $8000?$ 9fff. although this memory has 8,192 bytes available, the o sd module will use only 6, 528 bytes starting with the osd data in address range $8000 ?$91ff, followed by the cc data in address range $9200?$997f. see figure 17-9 . figure 17-9. osd flash memory map char1: high byte char1: low byte osd characters cc basic cc extended $8000 $8001 $91ff $9200 $96ff $9700 $997f total = 6528 bytes 4608 bytes characters 128 x 10 bytes characters 64 x 10 bytes on-screen display module (osd) flash programm ing guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 235 osd characters are stored in 12 x 18 matrices. each matrix row needs two bytes of storage sp ace, one byte for the ei ght left-hand pixels and another byte for the four right-h and pixels; therefore, each osd character takes up 36 bytes (see figure 17-10 ). the osd pixel matrix can be arbitrarily defined, except for the first two characters, which are always interpreted as border and background spaces and should be left empty. figure 17-10. osd pixel ma trix in flash memory although the cc pixe l matrix size is 9 x 13, it is not necessary to store the whole matrix in memory because: 1. with very few exceptions (the six box making characters of the closed-caption standard) there is no need to form composite characters by abutment on the horizontal or vertical directions. the exceptions are treated by the output logic. 2. the last two lines can only be occupied by underline pixels, which are automatically insert ed by the output logic. advance information mc68hc908tv24 ? rev. 2.1 236 on-screen display module (osd) freescale semiconductor on-screen display module (osd) as a consequence, only a reduced 8 x 10 matrix must be stored in the flash memory (see figure 17-11 ). the first two ch aracters are border and background spaces, so they must be left empty. also, since the output logic must give special treatment to the six box making characters, they must be stored right after the two space characters and their pixel matrices must be identical to those shown in figure 17-12 . figure 17-11. cc pixel ma trix in flash memory on-screen display module (osd) flash programm ing guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 237 figure 17-12. spaces and box-making charact ers in cc mode advance information mc68hc908tv24 ? rev. 2.1 238 on-screen display module (osd) freescale semiconductor on-screen display module (osd) figure 17-13 shows the overall organiza tion of the osd flash memory. the osd portion is organized as 18 consecutive blocks of 256 bytes. each block contains one pi xel matrix line of each of the 128 characters. each line of each characte r uses two bytes. the first byte has the eight left-hand pixels of the line, w hereas the second byte contains the four right-hand pixels. the cc portion is organized as 10 cons ecutive blocks of 128 bytes, each byte being a line of a basic cc character, plus 10 consecutive blocks of 64 bytes, each byte being a li ne of an extended cc character. figure 17-13. pixel matr ices organization in flash osd char 1 osd char 2 osd char 128 cc char 1 cc char 2 cc char 128 cc char 1 ext cc char 2 ext cc char 64 ext $8000 $91ff $9200 $96ff $9700 $997f osd data cc data extended cc data $9100 $9680 $80ff $927f $973f $9940 on-screen display module (osd) programming guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 239 17.7 programming guidelines this information is avai lable to the programmer for characterization of the displayed row: the vertical and horizontal placem ent of the active display area the scan line number within the active display area on which the character row is to start the displaying mode for the row: cc mode or osd mode if in osd mode, the characte r size from three choices these attributes that should be applied on the characters of the row: ? cc mode: rounding, black outl ine, underline, italics, and blinking ? osd mode: rounding, bla ck outline, blinking, and shadow the region of scan lines of the row to display the foreground color from 16 choices the background color from 16 choices a string of up to 34 ch aracters or control codes in addition, several control registers gover n when and how the osd interacts with the rest of the system. 17.7.1 setup initializing the osd involves enabling the appropriate modules, identifying the tv system, defining how interrupts ar e to be used, enabling outputs, defining the active levels of both inputs and outputs, and setting up the default display characteristics. for the osd to operate, the osd, pll, and dsl must be enabled. the pll provides clock signal synchro nized to the television chassis horizontal, and the dsl provides the field inform ation for interlacing. the pll has a startup time that must el apse before the osd should be used for display. advance information mc68hc908tv24 ? rev. 2.1 240 on-screen display module (osd) freescale semiconductor on-screen display module (osd) the received tv system must be identified in order to know if it is a 525-line or 625-line system. u pon identification, the ve rtical delay of the active display region should be pr ogrammed into the vertical delay register for proper c entering of the displa y. to help the software identifying the tv system, an interr upt is optionally generated at the starting edge of the vertical sync pul se. by measuring the time between two of these interrupts, it is possible to dist inguish between a 50-hz system (625 lines) and a 60-hz system (525 lines). after the identification, the interr upt can be disable by re setting the vsien bit on the enable cont rol register. if the elien bit of t he enable control register is set, the osd will generate an interrupt whene ver the target scan lin e defined in the event line register matches the current scan line count in the event register. the user can specify, with the xfer bi t in the enable cont rol register, if the osd transfers th e external rank of registers to the internal rank when the interrupt occurs. if transferring is not e nabled, then the osd is interrupting only to indicate a scan line match. tr ansferring must be enabled to display more than one row of characters. the active levels of hsync, vsync, fbkg, r, g, b, and i are all programmable. the character registers and display attri butes must be initialized, since most of these are undefined upon rese t. when the osd is disabled (osden = 0) and the pll is enabled (p llen = 1), writing to the external rank of r egisters also writes to the internal rank. the character registers should be set to $00 to indica te border space characters if no display is requir ed upon startup. the border color must be defined in the border control register. 17.7.2 interrupt servicing two possible sources of inte rrupt can be masked independently: vsync interrupt, gener ated at the starting edge of the internal vertical sync pulse. event line match interrupt, generat ed when the target scan line in the event line register matches the current scan line (event register). on-screen display module (osd) programming guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 241 upon receiving an interrupt , the cpu must read t he status register to identify the source of the interrupt and then clear the inte rrupt flags by writing any value into the status register. the flag bi ts corresponding to these interrupts are vs ynf (vsync flag) and el mf (event line match flag). if the received interrupt is an event line match interr upt, the cpu must update the information for the next row to be displayed. this information consists of: the display mode ( cc mode or osd mode) the target scan line the region of li nes to display character size (osd mode) character attributes valid for the entire row character codes and mi d-row attribute codes the display mode is programmed on bit 7 of the matrix st art register. the first scan line of the row is defined in the event line r egister. the region of lines to be displayed is programmed on matrix start register and matrix end register. note: if the value programmed on the event line register c auses the first line of the row to be after the last line of the tv pict ure, no elmf interrupt will be issued because the inte rnal line counter will never reach the value programmed on the register. the attributes for the characters of the row are defined using the foreground and background control regist ers, except for blinking, which is defined in the matr ix start register. the character codes and the mid-row attribute codes are stored in character register 1 to 34. si nce in osd mode a maximum of 24 characters can be displayed, it is not necessary to writ e all 34 character registers. however, the internal ci rcuit will try to read up to three consecutive control characters past t he last displayed character, in order to catch possible attribute changes after the end of the row. as a consequence, if less than three control charac ters (or none) will be advance information mc68hc908tv24 ? rev. 2.1 242 on-screen display module (osd) freescale semiconductor on-screen display module (osd) written after the end of the row, it is recommen ded to write at least one non-control character (anyone) terminating the sequence. the worst-case time for updating the registers occurs when displaying two vertically neighbor rows. in a 525-line sy stem with a 15,734-hz line-rate, this interval is approximately 826 s. if the next row to be displayed is not immediately below the current one, this time interval is larger. 17.7.3 software controlled features two features included into th e osd need software support: soft scrolling blinking. soft scrolling is accompli shed by manipulating the event line r egister, the matrix start regist er and the matrix end register on a periodic basis. the event line register contains the ta rget scan line and should be gradually decreased to scroll a display up t he screen. the matrix start register contains the starting line and the matri x end register co ntains the ending line of a row display. when scrolling up from the bottom of the screen, the range of lines should be gradually increased from the top line of the row. when scrolling up off the top of the screen, the range of lines should be gradually decreased to the bottom line of the row. blinking text is achieved by us ing mid-row contro l codes and the blinken bit in the border control regi ster. blinking text is designated by a preceding control code characte r with the blink bit set, and a following control code wi th blink cleared. the designated text will be replaced with backgrou nd space characters w henever the blinken bit is set, so toggling this bit at the desired blinki ng rate will produce the blinking effect on the text. 17.8 input and output the osd has 11 dedicated pins. se ven of them are digital cmos compatible signals. tw o are dedicated power pins for the analog part, and two are external filt er pins for the pll. on-screen display module (osd) input and output mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 243 17.8.1 power supply pins v ddosd and v ssosd are two dedicated power pi ns that feed the analog circuits contained in the osd and the dsl. these pins are provided to improve noise immunity of the analog circuits. 17.8.2 input pins the input pins are hsync and vsy nc. these inputs provide the horizontal and vertical ti ming reference from the external video system. both pins have internal schmitt tri ggers to improve noise immunity. the hinv and vinv bits in the out put control register sele ct the polarity of the hsync and vs ync inputs. 17.8.3 pll filter pins pins osdvco and osdp mp are used to tailor the 14-mhz pll loop filter and center frequency. the recommended filter ci rcuit for the pll is shown in figure 17-14 . figure 17-14. pll filter circuit osdvco osdpmp 4.7 k ? 470 nf advance information mc68hc908tv24 ? rev. 2.1 244 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.8.4 output pins the output pins are r, g, b, i, and fbkg. signals r, g, and b are the red, green, and blue colo r-encoded pixel si gnals that form the characters to be displayed. the polar ity of these bits is de termined by the cinv bit in the output control register. the fbkg (fast blanking) signal is intended to blank t he external video source so that the combinati on of osd and exte rnal video is non-additive. fbkg is asserted in five places: character foreground character roundi ng, if enabled character black outli ne or shadow, if enabled character background, if not transparent border, if not transparent the fbinv bit in the out put control register det ermines fbkg output polarity. the i (intensity) pin is in tended to control the in tensity of r, g, and b outputs, expanding the color palette to 16 colors. the iinv bit in the output control register det ermines i output polarity. 17.9 registers the osd has 46 register s, 38 of which are doubl e-ranked to prevent cpu access from distur bing the video display. on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 245 17.9.1 osd character registers the 34 double-ranked character register s contain character or control codes of an entire row. a character co de specifies a pos ition of the cc rom or the osd rom, depending on the displa y mode programmed on the dmode bit of the matr ix start register. a video control character is used to modify display at tributes in the middle of the row. the control character behaves differently and it s bits have different meanings, depending on the display mode. ch7 ? character bit 7 this is a control bit that determines whether ch[6:0] is interpreted as a normal character code or a code with special meaning: 1 = ch[6:0] has a different meaning depending on the display mode 0 = ch[6:0] is a character code. ch[6:0] ? character bits 6 to 0 these seven bits contain context d ependent information. if ch7 is 1, ch[6:0] is a special code that must be interpreted differently depending on the display mo de. in osd mode, it is always a control code that specifies mid-row changes in attributes. in cc mode, it may specify an attribute change or ma y contain a character of the extended set of 64 characters. if ch7 is 0, ch[6:0] is a normal character code specifying one of the 128 osd-rom characters, or one of the 128 non-extended cc-rom characters. address: $0020?$0041 bit 7654321bit 0 read: ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 write: reset: unaffected by reset figure 17-15. osd ch aracter registers (osdchar1?osdchar34) advance information mc68hc908tv24 ? rev. 2.1 246 on-screen display module (osd) freescale semiconductor on-screen display module (osd) in closed-caption mode, a contro l character is displayed as a background space, except when it c ontains an extended character. the formats shown in figure 17-16 , figure 17-17 , and figure 17-18 are valid only in cc mode. ech[5:0] ? extended character bits these six bits specify an address of the extended pa ge of the cc rom. ital ? italics bit determines when characters are di splayed in italics by slanting. 1 = subsequent foregr ound will be italicized 0 = subsequent foregro und will not be italicized bit 7654321bit 0 read: 1 0 ech5 ech4 ech3 ech2 ech1 ech0 write: reset: unaffected by reset figure 17-16. cc mode control char acter ? format a bit 7654321bit 0 read: 1 1 0 ital undl fgr fgb fgg write: reset: unaffected by reset figure 17-17. cc mode control char acter ? format b bit 7654321bit 0 read: 1 1 1 blink bks bkr bkb bkg write: reset: unaffected by reset figure 17-18. cc mode control char acter ? format c on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 247 undl ? underline bit this bit determines if characters are underlined. 1 = subsequent charac ters are underlined. 0 = subsequent charac ters are not underlined. fgr, fgb, and fgg ? foreground color bits these bits define the foreground colo r for the subsequent characters being displayed. the intensity of t he foreground color in cc mode is not modifiable inside the row. bit fgi of the foreground control register sets the foreground colo r intensity for the entire row. blink ? foreground blink bit determines, in conjunction with the blinken bit in the border control register, which text is blinking on the screen. the blinken bit is toggled, through soft ware, at the desir ed blinking frequency. foreground text (including underline) that is pr eceded by blink will flash at the bl inken frequency. 1 = subsequent foregr ound will be replaced by background color when blinken = 1. 0 = subsequent foregr ound will not blink. bks ? background solid bit this bit determines whether the backg round is transpar ent or visible. 1 = the background is a solid co lor determined by bkr, bkb, and bkg 0 = the background is transparent bkr, bkb, and bkg ? backgro und color bits these bits define the ba ckground color for the subsequent characters being displayed. bks mu st be set to displa y a background color. the intensity of the background color in cc mode is not m odifiable inside the row. bit bki of the backgr ound control regist er sets the background color intensit y for the entire row. in on-screen displa y mode, up to two consecutiv e control characters can be placed together without introducing a space on the screen. therefore, attributes belonging to different registers can be modified on a character by character basis inside words. the control character bits in osd mode are defined in figure 17-19 , figure 17-20 , and figure 17-21 . advance information mc68hc908tv24 ? rev. 2.1 248 on-screen display module (osd) freescale semiconductor on-screen display module (osd) bs ? back space bit determines if the next character is going to be displa yed on top of the preceding one. if this bi t is set, there can be only one contro l character between the two characters that are to be overlaid. the second character will not have black-out line or shadow and only its foreground color and intensity can be modified. if bs is set, the foreground color specified in this register applies only to the character to be overlaid and not to subsequent characte rs of the row. an example of overlay is shown in figure 17-18 . 1 = the next character will be overla id on top of the preceding one. 0 = the next character wi ll not be overlaid. bit 7654321bit 0 read: 1 0 bs ovm fgi fgr fgb fgg write: reset: unaffected by reset figure 17-19. osd mode cont rol character ? format a bit 7654321bit 0 read: 1 1 0 bks bki bkr bkb bkg write: reset: unaffected by reset figure 17-20. osd mode cont rol character ? format b bit 7654321bit 0 read: 111 blink shad1 shad0 write: reset: unaffected by reset = unimplemented figure 17-21. osd mode cont rol character ? format c on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 249 ovm ? overlay method bit if bs = 1, this bit determines how the second character will be overlaid on top of the first one. 1 = the rgb of the resulting foregr ound pixels will be the x-or of the individual rgb foreground pi xels, and the background will be the background of the first character. 0 = the foreground pixe ls of the second ch aracter will take precedence over the fo reground pixels of the first character, and the background w ill be the background of the first character. fgi ? foreground intensity bit this bit determines the intens ity of the foreground color. 1 = subsequent foreground pixels will have full intensity. 0 = subsequent foreground pixe ls will have half intensity. fgr, fgb, and fgg ? foreground color bits these bits define the foreground colo r for the subsequent characters being displayed. bks ? background solid bit determines whether the backgrou nd is transparent or visible. 1 = the background is a solid co lor determined by bkr, bkb, and bkg. 0 = the background is transparent. bki ? background intensity bit this bit determines the intens ity of the background color. 1 = subsequent backg round pixels will have full intensity. 0 = subsequent backg round pixels will have half intensity. bkr, bkb, and bkg ? backgro und color bits these bits define the ba ckground color for the subsequent characters being displayed. advance information mc68hc908tv24 ? rev. 2.1 250 on-screen display module (osd) freescale semiconductor on-screen display module (osd) blink ? blink foreground bit this bit determines, in conjunction with the bli nken bit in the border control register, which text is b linking on the scr een. the blinken bit is toggled, through software, at the desired bl inking frequency. foreground text that is preceded by blink will flash at the blinken frequency. 1 = subsequent foregr ound will be replaced by background color when blinken = 1. 0 = subsequent foregr ound will not blink. shad1 and shad0 ? s hadow control bits these bits specify the type of shadow that will be applied to subsequent foregr ound characters. table 17-1. shad1 and shad0 meaning shad1 and shad0 action 00 no shadow will be applied, but will be black-outlined if boen = 1 01 northwest shadow 10 not-pressed 3d shadow 11 pressed 3d shadow on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 251 17.9.2 osd vertical delay register this register defin es the vertical initial positi on in the active display area, as shown in figure 17-2 . the position is specifie d in number of lines from the starti ng edge of vsync. the position of the active display area should be centered on the screen by software according to the tv standard being rece ived (525 or 625 lines). by adjusting t he vertical position in this r egister, it is not necessary to consider different tv system timings when programming the event line register. vd[5:0] ? vertical delay bits number of lines from the starting edge of vsync until the beginning of the active display area address: $0042 bit 7654321bit 0 read: 0 0 vd5 vd4 vd3 vd2 vd1 vd0 write: reset:00000000 = unimplemented figure 17-22. osd vert ical delay register (osdvdr) advance information mc68hc908tv24 ? rev. 2.1 252 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.9.3 osd horizontal delay register this register defines the horizontal delay of the active display area with respect to the st arting edge of the internal (c onditioned with hinv bit) hsync. each increment prov ides approximately 0.14 s of delay, regardless of the character size programmed in the chhs and chws bits. in addition to the specified delay, there is a built-in fixed delay of approximately 14.1 s. hd[4:0] ? horizontal delay bits these bits define the horizontal delay of the active display area from the starting edge of hsync. 17.9.4 osd foreground control register this double-ranked r egister is used to define character row attributes prior to display of the row. with the exception of c hhs and chws, all attributes defined by this register are applicable to both cc mode and osd mode. the character size c an be changed only in osd mode. the foreground color can be changed mid-row by th e use of control address: $001b bit 7654321bit 0 read: 0 0 0 hd4 hd3 hd2 hd1 hd0 write: reset:00000000 = unimplemented figure 17-23. osd hori zontal delay register (osdhdr) on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 253 characters. the intensity of the color, defined by bit fgi, can be modified mid-row only in osd mode. chhs ? character height select bit this bit determines whethe r characters in osd m ode are displayed at standard height and width, or at double height wi th width selected by chws. character height is selected for an entire row. 1 = 2x height characters, chws will determine the character width 0 = standard size (height and width) characters chws ? character width select bit this bit determines the character width when chhs = 1. character width is selected for an entire row. 1 = 2x width characters are selected. 0 = 1.5x width characters are selected. rnden ? rounding enable bit this bit determines if for eground characters are rounded. 1 = foreground will be rounded. 0 = foreground will not be rounded. boen ? black outline enable bit this bit determines if foreground c haracters are black outlined when shadow is disabled (shad1 = 0 and shad2 = 0). shadow takes precedence over black outline. if any of the forms of shadow is set, the character will not be black outlined. 1 = foreground characte rs are black outlined if shadow is disabled. 0 = foreground characters are not black outlined. address: $001c bit 7654321bit 0 read: chhs chws rnden boen fgi fgr fgb fgg write: reset:00000000 figure 17-24. osd fore ground control register (osdfcr) advance information mc68hc908tv24 ? rev. 2.1 254 on-screen display module (osd) freescale semiconductor on-screen display module (osd) fgi ? foreground intensity bit this bit determines the intens ity of the foreground color. 1 = foreground pixels will have full intensity. 0 = foreground pixels will have half intensity. fgr, fgb, and fgg ? foreground color bits these bits define the foreground colo r for the characte rs of the row. 17.9.5 osd background control register this double-ranked r egister is used to define character row attributes prior to display of the row. the shadow attribut e is only applicable to osd mode and is ignored in cc mode. the rest of the attributes are applicable to both modes. the ba ckground color can be changed mid-row by the use of control characte rs, but the intensity of the color, defined by bit bki, can be m odified mid-row in osd mode only. when background is transparent, the vi deo image that substitutes it can be attenuated by setting bit bkh t. this setting cannot be changed mid-row. bkht ? background half-tone bit this bit controls the video intensity when transparent background is selected. 1 = video will be attenuated in transparent areas. 0 = video will not be attenuated. address: $001d bit 7654321bit 0 read: bkht shad1 shad0 bks bki bkr bkb bkg write: reset:00000000 figure 17-25. osd ba ckground control register (osdbkcr) on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 255 shad1 and shad0 ? s hadow control bits these bits specify the type of sh adow that will be applied to all characters of the row. table 17-1 gives the meaning of these bits. bks ? background solid bit this bit determines whether the backg round is transpar ent or visible. 1 = background is a solid colo r determined by b kr, bkb, and bkg. 0 = background is transparent. bki ? background intensity bit this bit determines the intens ity of the background color. 1 = row background color wi ll have full intensity 0 = row background color will have half intensity bkr, bkb, and bkg ? backgro und color bits these bits define the row background color. 17.9.6 osd border control register this register is us ed to define border characteristics. blinken ? blink enable bit this bit determines if text following a control code with blink set will be displayed. blinken should be toggled in software to establish the desired blinking frequency. 1 = text following a control c ode with blink se t will not be displayed. 0 = text following a control code with blink set wi ll be displayed. address: $0043 bit 7654321bit 0 read: blinken boht vmute bos boi bor bob bog write: reset:00000000 figure 17-26. osd bor der control register (osdbcr) advance information mc68hc908tv24 ? rev. 2.1 256 on-screen display module (osd) freescale semiconductor on-screen display module (osd) boht ? video tone bit this bit controls the video intensity when transparent background or transparent border is selected. 1 = video will be attenuated in transparent areas. 0 = video will not be attenuated. vmute ? video muting bit this bit controls the vi deo muting function, in which the whole screen is filled with a solid color. 1 = the whole screen is filled with a solid color determined by bor, bob and bog 0 = the screen is enabl ed to show video, osd, and caption. bos ? border solid bit this bit determines whether the bor der is transparent or visible. 1 = the border is a solid color determined by bor, bob, and bog. 0 = the border is transparent. boi ? border intensity bit this bit determines the int ensity of the border color. 1 = border pixels wi ll have full intensity. 0 = border pixels wi ll have half intensity. bor, bob, and bog ? border color bits these bits define the border color. on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 257 17.9.7 osd enable control register this register contai ns enable and control bits for the osd. osden ? osd enable bit this bit determines whether the osd is enabled or disabled. the pllen bit must also be set for osd operation, and the dsl must be enabled to provide field in formation for interlacing. 1 = osd enabled 0 = osd disabled elien ? event line matc h interrupt enable bit this bit determines if the elmf bit in the status register is enabled to generate interrupt requests to the cpu. 1 = event line match interrupt enabled 0 = event line match interrupt disabled vsien ? vertical sync interrupt enable bit this bit determines if the vsinf bit in the status register is enabled to generate interrupt requests to the cpu. 1 = vertical sync interrupt enabled 0 = vertical sync interrupt disabled xfer ? external to inter nal rank transfer enable bit this bit determines if the external rank of regi sters is transferred to the internal rank upon an event line match. 1 = transfer enabled 0 = transfer disabled address: $fe0b bit 7654321bit 0 read: osden elien vsien xfer pllen mem1 mem0 scan write: reset:00000000 figure 17-27. osd e nable control register (osdectr) advance information mc68hc908tv24 ? rev. 2.1 258 on-screen display module (osd) freescale semiconductor on-screen display module (osd) pllen ? pll enable bit this bit determines if the phase-lo cked loop oscillator is enabled. when enabling the pll, the program must wait fo r the pll to stabilize before activating the osd to achieve a stable display. the pll should be disabled before stop m ode is entered. in addi tion, it may be useful to stop the pll whenever osd data are not curr ently being displayed, to eliminate ingress of 14-mhz interference to the rf, if, or base-band portions of the external video chain. 1 = pll enabled 0 = pll disabled mem[1:0] ? memo ry test mode bits these two bits can only be accessed in peripheral test mode (ptm) or cpu test mode (ctm ). they allow to choose one of the two character register ranks to be directly connected to the internal bus, bypassing the internal osd control. table 17-2 shows the meaning of these bits. scan ? scan test mode bit this bit also can be accessed only in one of the test modes. it causes the osd module to reconf igure some of its inter nal circuitry to prepare itself for production test. 1 = osd module is reconfi gured to production test. 0 = osd module keeps it s functional structure. table 17-2. memory test mode bits mem[1:0] what can be accessed via internal bus 00 | 01 one of the character-register ranks, determined by the internal osd circuitry; functional behavior 10 character registers ? rank 1 11 character registers ? rank 2 on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 259 17.9.8 osd event line register this register contains th e target scan line address fo r the next row to be displayed. the range of li nes considered for displa y is inside the active display area, as shown in figure 17-2 . writing a 0 into the event line register means that the row should be displayed at the first line of the active display area. the vertical plac ement of the acti ve area must be adjusted using the vert ical delay register. el[7:0] ? event line number bits these bits define where to display the first scan line of the next character row. note: if the value programmed on the event line register c auses the first line of the row to be after the last line of the tv pict ure, no elmf interrupt will be issued because the inte rnal line counter will never reach the value programmed on the register. address: $0044 bit 7654321bit 0 read: el7el6el5el4el3el2el1el0 write: reset:00000000 figure 17-28. osd e vent line register (osdelr) advance information mc68hc908tv24 ? rev. 2.1 260 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.9.9 osd event count register this read-only register make s the internal scan line counter visible to the cpu. ev[7:0] ? event count bits these bits mirror the internal scan line counter contents. 17.9.10 osd output control register this register contains c ontrol bits for t he input and output pins of the osd. hinv ? hsync polarity bit this bit determines whether the hsync input is ac tive low or active high. 1 = hsync input is active low and is inverted internally. 0 = hsync input is active high. address: $0045 bit 7654321bit 0 read: ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 write: reset: unaffected by reset = unimplemented figure 17-29. osd e vent count register (osdecr) address: $fe0a bit 7654321bit 0 read: 0 hinv vinv fdinv cinv fbinv iinv 0 write: reset:00000000 = unimplemented figure 17-30. osd outp ut control register (osdocr) on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 261 vinv ? vsync polarity bit this bit determines whether the vsync input is ac tive low or active high. 1 = vsync input is active low and is inverted internally. 0 = vsync input is active high. fdinv ? field invert bit this bit determines whether the odd/ev en field indicator from the data slicer is inverted or not inverted. 1 = odd/even field i ndicator from the data slicer is inverted. 0 = odd/even field indi cator from the data slicer is not inverted. cinv ? color invert bit this bit determines whether the r, g and b outputs are active low or active high. 1 = r, g, and b output s are active low. 0 = r, g, and b output s are active high. fbinv ? fast blanking invert bit this bit determines whether the fbkg output is active low or active high. 1 = fbkg output is active low. 0 = fbkg output is active high. iinv ? intensity invert bit this bit determines whether the intens ity output (i) is active low or active high. 1 = i output is active low. 0 = i output is active high. advance information mc68hc908tv24 ? rev. 2.1 262 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.9.11 osd status register this register contains t he interrupt flags and provid es visibility of the input signals. elmf ? event line match interrupt bit this bit is set when the current fiel d scan line (event register) matches the target field scan line (event line r egister). it will cause an interrupt if the elien bit is set in the enable control register. the interrupt must be acknowledged by writing any value to the register. vsinf ? vertical sync interrupt bit this bit is set at ev ery starting edge of vsync . it will cause an interrupt if the vsien bit is set in the enabl e control register. the interrupt must be ackn owledged by writing any value to the register. hsyn ? horizontal sync pulse bit this read-only bit provi des visibility to the hsync input. a logic 1 indicates the presence of a horizontal sync pulse. vsyn ? vertical sync pulse bit this read-only bit provi des visibility to the vsync input. a logic 1 indicates the presence of a vertical sync pulse. address: $0046 bit 7654321bit 0 read: elmf vsinf hsyn vsyn 0 vcotst dsltst plltst write: reset:00uu0000 = unimplemented figure 17-31. osd status register (osdsr) on-screen display module (osd) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 263 vcotst ? vco test mode bit this bit can be accessed only in peripheral test mod e (ptm) or cpu test mode (ctm). it is provided to facilitate the test of the vco circuit inside the osd-pll, allowing obser vation of the pll clock frequency through pin fbkg. 1 = a signal with half of the pll clock frequency is connected to pin fbkg. 0 = the fast blanking si gnal goes to fbkg. dsltst ? data slicer test mode bit this bit also can be accessed only in one of the test modes. it is used to reconfigure the analog part of the data slicer (dsl) circuit to allow its own test. 1 = dsl is put into test mode 0 = dsl is in functional mode plltst ? pll test mode this bit also can be accessed only in one of the test modes. it is used to reconfigure the osd-p ll to allow its own test. 1 = osd-pll is put into test mode. 0 = osd-pll is in functional mode. 17.9.12 osd matrix start register this double-ranked r egister defines the disp lay mode, the blinking attribute and the first line of the ro w to be displayed. the display mode, either cc or osd, defi nes the size of the pixe l matrix, what character rom should be fetched, and what attributes ca n be applied to the characters along the row. it also def ines how mid-row control characters must be interpreted. the blinking attribute can be modified mid-row by control characters. advance information mc68hc908tv24 ? rev. 2.1 264 on-screen display module (osd) freescale semiconductor on-screen display module (osd) dmode ? display mode bit thie bit defines the size of the pixel matrix, what character rom should be fetched a nd what attributes can be applied to the characters along the row. 1 = row will be di splayed in cc mode 0 = row will be di splayed in osd mode blink ? blink foreground bit this bit determines, in conjunction with the bli nken bit in the border control register, which text is b linking on the scr een. the blinken bit is toggled, through software, at the desired bl inking frequency. if blink is set in this r egister, the whole row wil l flash at the blinken frequency. 1 = the entire row will be replac ed by background color when blinken = 1 0 = the row will not blink ms[4:0] ? matrix start line bits these bits set the starting scan line within the character row. ms[4:0] = 0 means that the row starts at the first scan line. valid start numbers are 0 through 12 in cc mode and 0 through 17 in osd mode. address: $001e bit 7654321bit 0 read: dmode blink 0 ms4 ms3 ms2 ms1 ms0 write: reset:00000000 = unimplemented figure 17-32. osd ma trix start register (osdmsr) on-screen display module (osd) low power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor on-screen display module (osd) 265 17.9.13 osd matrix end register this double-ranked r egister defines the last line of the row to be displayed. me[4:0] ? matrix end line bits these bits set the ending scan line within the c haracter row. in cc mode, valid numbers are 0 through 12, and me[4:0] = 12 means that the row is displayed through its la st scan line. in osd mode, valid numbers are 0 through 17, and me[4:0] = 17 mean s that the row is displayed through its last scan line. 17.10 low power modes the wait and stop instruct ions put the mcu in low power-consumption standby modes. 17.10.1 wait mode the osd remains active during wait mode, but it will be unable to interrupt the cpu and bring it out of this mode. it is recommended that the osd and pll be disabled before entering wait mode, unless a single row of fixed video output is desired to be displayed constantly. address: $001f bit 7654321bit 0 read: 0 0 0 me4 me3 me2 me1 me0 write: reset:00000000 = unimplemented figure 17-33. osd ma trix end register (osdmer) advance information mc68hc908tv24 ? rev. 2.1 266 on-screen display module (osd) freescale semiconductor on-screen display module (osd) 17.10.2 stop mode although the osd module and the pll are no t automatically disabled in stop mode, the flash me mory will be disabled. as a consequence, the osd module will not work. it is recommended that the osd and pll be disabled before entering stop mode. 17.11 interrupts and resets the osd has two sources of interrupt s: the elmf and vsinf flags in the osd status regist er. these interrupts c an be independently masked by bits elien and vsi en in the osd enable c ontrol register. both interrupts will cause the cpu to ve ctor to the address stored in $ffee?$ffef. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor input/output (i/o) ports 267 advance information ? mc68hc908tv24 section 18. input/output (i/o) ports 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 18.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 18.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 270 18.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 18.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 18.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2 introduction twenty-one (21) bidirectional input-out put (i/o) pins fo rm three parallel ports. all i/o pins are progr ammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. advance information mc68hc908tv24 ? rev. 2.1 268 input/output (i/o) ports freescale semiconductor input/output (i/o) ports addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 269. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 272. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 274. read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 270. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 273. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 275. read: 0 0 0 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 18-1. i/o port register summary input/output (i/o) ports port a mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor input/output (i/o) ports 269 18.3 port a port a is an 8-bit, general-pur pose, bidirectional i/o port. 18.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 18-2. port a data register (pta) advance information mc68hc908tv24 ? rev. 2.1 270 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 18.3.2 data direction register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. ddra7?ddra0 ? data direc tion register a bits these read/write bits control port a data direction. reset clears ddra7?ddra0, configuring al l port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 18-4 shows the port a i/o logic. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 18-3. data direct ion register a (ddra) input/output (i/o) ports port a mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor input/output (i/o) ports 271 figure 18-4. port a i/o circuit when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 18-1 summarizes the operation of the port a pins. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus table 18-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) input, hi-z (2) ddra7?ddra0 pin pta7?pta0 (3) 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. advance information mc68hc908tv24 ? rev. 2.1 272 input/output (i/o) ports freescale semiconductor input/output (i/o) ports 18.4 port b port b is an 8-bit, general-pur pose, bidirectional i/o port. 18.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 18-5. port b data register (ptb) input/output (i/o) ports port b mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor input/output (i/o) ports 273 18.4.2 data direction register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. ddrb7?ddrb0 ? data direc tion register b bits these read/write bits control port b data direction. reset clears ddrb7?ddrb0, configuring al l port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 18-7 shows the port b i/o logic. figure 18-7. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 18-6. data direct ion register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus advance information mc68hc908tv24 ? rev. 2.1 274 input/output (i/o) ports freescale semiconductor input/output (i/o) ports when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 18-2 summarizes the operation of the port b pins. 18.5 port c port c is a 5-bit, general-pur pose, bidirectional i/o port. 18.5.1 port c data register the port c data register (ptc) contains a data latch for each of the five port c pins. table 18-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) input, hi-z (2) ddrb7?ddrb0 pin ptb7?ptb0 (3) 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. address: $0002 bit 7654321bit 0 read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset = unimplemented figure 18-8. port c data register (ptc) input/output (i/o) ports port c mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor input/output (i/o) ports 275 ptc4?ptc0 ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 18.5.2 data direction register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. ddrc4?ddrc0 ? data direc tion register c bits these read/write bits control port c data direction. reset clears ddrc4?ddrc0, configuring al l port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 18-10 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: 0 0 0 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 18-9. data direct ion register c (ddrc) advance information mc68hc908tv24 ? rev. 2.1 276 input/output (i/o) ports freescale semiconductor input/output (i/o) ports figure 18-10. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 18-3 summarizes the operation of the port c pins. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus table 18-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) input, hi-z (2) ddrc4?ddrc0 pin ptc4?ptc0 (3) 1 x output ddrc4?ddrc0 ptc4?ptc0 ptc4?ptc0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor random-access memory (ram) 277 advance information ? mc68hc908tv24 section 19. random-access memory (ram) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 19.2 introduction this section describes the 602 by tes of ram (random-access memory). 19.3 functional description addresses $0050 through $02 af are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. advance information mc68hc908tv24 ? rev. 2.1 278 random-access memory (ram) freescale semiconductor random-access memory (ram) during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 279 advance information ? mc68hc908tv24 section 20. system integration module (sim) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 20.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 283 20.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . 284 20.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 284 20.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 284 20.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 286 20.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 20.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 288 20.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 20.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .289 20.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 289 20.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 20.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 289 20.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 290 20.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 290 20.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 20.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 20.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 20.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 20.6.1.3 interrupt status r egisters . . . . . . . . . . . . . . . . . . . . . . .294 20.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 20.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 20.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 296 20.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 20.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 advance information mc68hc908tv24 ? rev. 2.1 280 system integration module (sim) freescale semiconductor system integration module (sim) 20.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 300 20.8.2 sim reset status regist er . . . . . . . . . . . . . . . . . . . . . . . . 301 20.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . .303 20.2 introduction this section describes the system integration module (sim). together with the cpu, the sim cont rols all mcu activities. a block diagram of the sim is shown in figure 20-1 . table 20-1 is a summary of the sim input/output (i/o) regist ers. the sim is a system state controller that coordinates cpu and exception ti ming. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing table 20-1 shows the internal signal na mes used in this section. system integration module (sim) introduction mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 281 figure 20-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 table 20-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal advance information mc68hc908tv24 ? rev. 2.1 282 system integration module (sim) freescale semiconductor system integration module (sim) addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 300. read: rrrrrr sbsw r write: note reset:00000000 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) see page 301. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 sim upper byte address register (subar) read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) see page 303. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 295. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 295. read: 00000if9if8if7 write:rrrrrrrr reset:00000000 = unimplemented figure 20-2. sim i/o register summary system integration module (sim) sim bus clock control and generation mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 283 20.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 20-3 . this clock can come from either an exte rnal oscillator or from the on-chip pll. (see section 7. clock gene rator module (cgmc) .) figure 20-3. cgm clock signals 2 bus clock generators sim sim counter monitor mode user mode oscillator (osc) osc2 osc1 phase-locked loop (pll) cgmxclk cgmrclk it12 cgmout simdiv2 ptc3 to timebase module to rest of chip it23 to rest of chip advance information mc68hc908tv24 ? rev. 2.1 284 system integration module (sim) freescale semiconductor system integration module (sim) 20.3.1 bus timing in user mode , the internal bus fr equency is either t he crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see section 14. external interrupt (irq) . 20.3.2 clock startup from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripheral s are inactive and held in an inactive phase unt il after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon comp letion of the timeout. 20.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows cgmxclk to clock the sim coun ter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 20.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 20.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhi bit module (lvi) illegal opcode illegal address system integration module (sim) reset and system initialization mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 285 all of these resets produce the vector $fffe :$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clears the sim counter (see 20.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register ( srsr). (see 20.8 sim registers .) 20.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cg mxclk cycles, assuming t hat neither the por nor the lvi was the sour ce of the reset. see table 20-2 for details. figure 20-4 shows the relative timing. figure 20-4. exter nal reset timing table 20-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout advance information mc68hc908tv24 ? rev. 2.1 286 system integration module (sim) freescale semiconductor system integration module (sim) 20.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additional 32 cycles. see figure 20-5 . an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lv i, or por. (see figure 20-6 .) note: for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the si m forces the rst pin low. the internal reset signal then follows the sequence fr om the falling edge of rst shown in figure 20-5 . figure 20-5. internal reset timing the cop reset is asynchro nous to the bus clock. figure 20-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low iab 32 cycles 32 cycles vector high cgmxclk by mcu illegal address rst illegal opcode rst coprst lvi por internal reset system integration module (sim) reset and system initialization mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 287 20.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cg mxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, thes e events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and m odules are held i nactive for 4096 cgmxclk cycles to al low stabilization of the oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 20-7. por recovery porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff advance information mc68hc908tv24 ? rev. 2.1 288 system integration module (sim) freescale semiconductor system integration module (sim) 20.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 4 of the sim counter. the s im counter output, which o ccurs at least every 2 13 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents t he cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 20.4.2.3 ille gal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bi t, stop, in the co nfiguration register is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. system integration module (sim) sim counter mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 289 20.4.2.4 ille gal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 20.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bi t in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu is released from re set to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 20.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter overflow supplies the cl ock for the cop module. the sim counter is 13 bits long and is clo cked by the falling edge of cgmxclk. 20.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enabl es the clock generation m odule (cgm) to drive the bus clock state machine. advance information mc68hc908tv24 ? rev. 2.1 290 system integration module (sim) freescale semiconductor system integration module (sim) 20.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register. if the ssrec bit is a lo gic 1, then the stop recovery is reduced from the no rmal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require lo ng startup times from stop mode. external crystal applicati ons should use the full st op recovery time, that is, with ssrec cleared. 20.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 20.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 20.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) 20.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts system integration module (sim) exception control mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 291 20.6.1 interrupts at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 20-8 shows interrupt entry timing. figure 20-9 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). (see figure 20-10 .) figure 20-8 . interrupt entry timing figure 20-9. interrupt recovery timing module idb r/ w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit advance information mc68hc908tv24 ? rev. 2.1 292 system integration module (sim) freescale semiconductor system integration module (sim) figure 20-10. inte rrupt processing no no no yes no no yes yes as many interrupts i bit set? from reset break i bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt? system integration module (sim) exception control mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 293 20.6.1.1 hard ware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 20-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 20-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine advance information mc68hc908tv24 ? rev. 2.1 294 system integration module (sim) freescale semiconductor system integration module (sim) note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 20.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 20.6.1.3 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 20-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 20-3. interrupt sources priority interrupt source interrupt status register flag highest reset ? swi instruction ? irq pin i1 pll i2 timebase module i3 tim channel 0 i4 tim channel 1 i5 ttim overflow i6 osd i7 dsl i8 lowest ssi i9 system integration module (sim) exception control mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 295 interrupt status register 1 i6?i1 ? interrupt flags 1?6 these flags indicate the presence of interrupt r equests from the sources shown in table 20-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 interrupt status register 2 i9?i7 ? interrupt flags 9?7 these flags indicate the presence of interrupt r equests from the sources shown in table 20-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe04 bit 7654321bit 0 read: i6 i5 i4 i3 i2 i1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 20-12. interrupt st atus register 1 (int1) address: $fe05 bit 7654321bit 0 read: 00000i9i8i7 write:rrrrrrrr reset:00000000 r= reserved figure 20-13. interrupt st atus register 2 (int2) advance information mc68hc908tv24 ? rev. 2.1 296 system integration module (sim) freescale semiconductor system integration module (sim) 20.6.2 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 20.6.3 break interrupts the break module ca n stop normal program flow at a software-programmable break point by asserting its break interrupt output. see section 6. break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 20.6.4 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2- step clearing mechanism ? for example, a read of one register followed by the read or write of a nother ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. system integration module (sim) low-power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 297 20.7 low-power modes executing the wait or stop instruction put s the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following subsecti ons. both stop and wait clear the interrupt mask (i) in the condition code register , allowing interrupts to occur. 20.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 20-14 shows the timing for wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register is logic 0, then the comp uter operating properly module (cop) is enabled and remains active in wait mode. figure 20-14. wait mode entry timing figure 20-15 and figure 20-16 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. advance information mc68hc908tv24 ? rev. 2.1 298 system integration module (sim) freescale semiconductor system integration module (sim) figure 20-15. wait recovery from interrupt or break figure 20-16. wait recovery from internal reset 20.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the clock generator module output (cgm out) in stop mode, stopping the cpu and peripherals 1 . stop recovery time is selectable using the ssrec bit in the configurati on register (config). if ssrec is set, stop recovery is r educed from the nor mal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng startup time s from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitsto pwait = rst pin, cpu interrupt, or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles 1. clock cgmxclk is not stopped. it c ontinues to feed the timebase module. system integration module (sim) low-power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 299 a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 20-17 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 20-17. stop m ode entry timing figure 20-18. stop m ode recovery from in terrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period advance information mc68hc908tv24 ? rev. 2.1 300 system integration module (sim) freescale semiconductor system integration module (sim) 20.8 sim registers the sim has three memory-mapped registers. table 20-4 shows the mapping of thes e registers. 20.8.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from stop mode or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt. 0 = stop mode or wait mode was not exited by break interrupt. table 20-4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset:00000000 r= reserved note: writing a logic 0 clears sbsw. figure 20-19. sim break status register (sbsr) system integration module (sim) sim registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 301 sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. writing 0 to the sb sw bit clears it. 20.8.2 sim reset status register this register contains si x flags that show the s ource of the last reset provided all previous reset status bi ts have been cleared. clear the sim reset status register by reading it . a power-on reset se ts the por bit and clears all other bits in the register. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 = unimplemented figure 20-20. sim reset st atus register (srsr) advance information mc68hc908tv24 ? rev. 2.1 302 system integration module (sim) freescale semiconductor system integration module (sim) por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr system integration module (sim) sim registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor system integration module (sim) 303 20.8.3 sim break flag control register the sim break control regist er contains a bit that enables software to clear status bits while t he mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 20-21. sim break flag control register (sbfcr) advance information mc68hc908tv24 ? rev. 2.1 304 system integration module (sim) freescale semiconductor system integration module (sim) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 305 advance information ? mc68hc908tv24 section 21. serial synchronous interface module (ssi) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 21.4 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 21.4.1 start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 21.4.2 slave address transmission . . . . . . . . . . . . . . . . . . . . . . .309 21.4.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 21.4.4 stop signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.5 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.6 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 21.4.7 clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5 programming guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5.1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 21.5.2 interrupt serving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 21.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 21.6.1 ssi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 21.6.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 21.6.3 ssi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 21.8 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 advance information mc68hc908tv24 ? rev. 2.1 306 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) 21.2 introduction the serial synchronous interface modul e (ssi) transmits and receives synchronous serial data for communic ation with other peripherals. it offers i 2 c master compatibility, taking care of start and stop signal generation and optionally producing byte-by-byte interrupts. the interface has two pairs of clock a nd data lines that can not operate simultaneously. in that way, sensitive devices can be isolated from each other by putting them in separate clock and data lines. 21.3 features the ssi has these key features: limited master compat ibility with the i 2 c bus standard high interference immunity bet ween the clock and data lines software programmable clock frequency software controlled acknowle dge bit generation/detection start and stop signal generation interrupt driven byte -by-byte data transfer repeated start signal generation clock stretching to allo w operation of slow devices serial synchronous interface module (ssi) overview mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 307 21.4 overview the ssi uses two serial data lines (sda1 and sda2) and two serial clock lines (scl1 and scl2) for data transfer. all devices connected in these lines must have open-drain or open-collector outputs. logic ?and? function is exercised on all four lines with external pullup resistors. only one pair of clock and data lines is allo wed to operate at any time. they share the same internal seri al-to-parallel converter (see figure 21-1 ). figure 21-1. ssi block diagram ack data register lsb msb sda1 sda2 scl1 scl2 clock control advance information mc68hc908tv24 ? rev. 2.1 308 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) the ssi can operate in master mode only , but it can send or receive data from peripherals. no rmally, a standard communi cation is composed of four parts: start signal, slave address transmission, data transfer and stop signal. the start and stop si gnals are generated by hardware under software control. slave addr ess transmission is viewed here as a normal data transmission. the data byte and the acknow ledge-bit must be written or read by software. an interrupt is optiona lly generated on a byte-by-byte basis to help data transfer. 21.4.1 start signal for sake of simplicity, the following te xt refers to either scl1 or scl2 as just scl, and sda1 or sad2 as just sda. to initiate a communication, the c pu will program the control and the data registers and then t he ssi will send a star t signal. as shown in figure 21-2 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may c ontain several byte s of data) and wakes up all slaves. figure 21-2. tr ansmission signal start signal read/write calling address ack bit data byte no ack bit stop signal scl sda serial synchronous interface module (ssi) overview mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 309 21.4.2 slave address transmission the first byte of data transfer immediat ely after the start signal is the slave address transmitted by the master . this is a 7-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer: 1 = read transfer, the slave transmits data to the master 0 = write transfer, the master transmits data to the slave only the slave with a calling address that matc hes the one transmitted by the master will respond by sendi ng back an acknowledge bit. this is done by pulling the sda low at the ninth clock (see figure 21-2 ). no two slaves in the system ma y have the same address. 21.4.3 data transfer once slave addre ssing is achieved successful ly, the data transfer can proceed byte-by-byte in a direction specified by t he r/w bit. all transfers that come afte r an address cycle are referr ed to as data transfers. each data byte is eight bits long. data may be changed only while scl is low and must be held stable wh ile scl is high as shown in figure 21-2 . there is one clock pulse on scl for each data bit, the msb being transferred first. each data byte ha s to be followed by an acknowledge bit, which is signaled from the receiving device by pulling the sda low at the ninth clock. so one complete data byte transfer needs nine clock pulses. if the peripheral does not acknowl edge the received byte, the sda line is left high during the acknowledge bit interval. the ssi can then generate a stop signal at t he end of the next data trans fer or a start signal (repeated start) to co mmence a new calling. if the ssi is operating as a receiv er and it does not acknowledge the slave transmitter after a byte transmission, it means ?end of data? to the slave. so, the slave releases th e sda line for the ssi to generate a stop or start signal. advance information mc68hc908tv24 ? rev. 2.1 310 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) 21.4.4 stop signal the ssi module can terminate t he communication by generating a stop signal that will fr ee the bus at the end of t he current byte transfer. however, the ssi may generate another start signal without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-high tr ansition of sda while scl is at logical 1 (see figure 21-2 ). the ssi module can generate a stop even if the peripheral has generated an acknowledge at which point the peri pheral must release the bus. 21.4.5 clock synchronization since wired-and logic is performed on the scl line, peri pherals can also drive the serial clock signal. a hi gh-to-low transiti on on the scl line affects all the devices connected on t he bus. the devices start counting their low period and once a device?s clo ck has gone low, it holds the scl line low until the clock high state is reached. however, the change of low to high in this de vice clock may not change t he state of the scl line if another device clock is st ill within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods ent er a high wait state dur ing this time. when all devices concerned have counted off t heir low period, the synchronized clock scl line is re leased and pulled high. 21.4.6 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hol d the scl low after completion of one byte transfer (nine bits). in su ch case, it halts the bus clock and forces the master clock into wait st ates until the slave releases the scl line. serial synchronous interface module (ssi) programming guidelines mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 311 21.4.7 clock stretching the clock synchronization mechanism ca n be used by sl aves to slow down the bit rate of a transfer. afte r the master has driven scl low, the slave can drive scl low for the requir ed period and then re lease it. if the slave scl low period is greater than the master scl low period, then the resulting scl bu s signal low period is stretched. 21.5 programming guidelines two modes of operation are possible: master transmitter master receiver in both modes, the program ming procedure is the sa me for the first byte, because the slave address is sent. afte r the first byte, the procedure is a little different in each case. 21.5.1 setup on both transmitter and receiver modes, a set up involves these steps: 1. enable the ssi and the interrupt s (if desired) in the control register. 2. program the desire d clock rate in t he control register. 3. set the start bit, reset the stop bit, and set the a ck bit so that it will lose any wired-and dispute. 4. write the slave addr ess and the r/w bit into the data register. since the sf flag is cl ear at reset, a write to the data register triggers the shifting of the data into the bus. advance information mc68hc908tv24 ? rev. 2.1 312 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) 21.5.2 interrupt serving the internal shift register is compos ed of the data regi ster and the ack bit, as shown in figure 21-1 . as the data is shift ed out (msb first), the signal on the data line, re sulting from the wired- and logic, will be shifted back to the register via least signific ant bit. at the end of the transfer, the contents of the data register and the ack bit of the control register reflect what was present in the external bus. in that way the cpu can read the data register and t he ack bit to find out the contents of the bus during the transfer. after the ninth scl fall ing edge, an interrupt will be generated (if enabled) and scl will stop until the interrupt is served by reading the status register and th en writing or reading the data register. in transmitter mode, upon receiving an interrupt, the cpu has to perform these tasks: 1. read the status register. 2. optionally, read t he ack bit to see if the peripheral has acknowledged the transmission. 3. optionally, read the data register to s ee if there was any contention on the bus, in which case the contents of the register would have changed. this operat ion clears the sf flag. 4. write into the data register th e next byte to be transmitted. this operation also clears the sf fl ag and initiates the data shifting. in receiver mode, upon receiving an in terruption, the cpu has to perform these tasks: 1. read the status register. this operation clears t he sf flag and the interrupt. 2. read the desired data in the data register. 3. write ?0? into the ack bit of the control register to acknowledge the reception of the next byte. 4. write $ff into the data register . this operation initiates the transfer of the next byte. serial synchronous interface module (ssi) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 313 21.6 registers three registers are used in the ssi module. the inte rnal configuration of these registers is discussed here. 21.6.1 ssi control register the ssi control register (ssicr) provides eight control bits. sie ? ssi interrupt enable bit this bit determines if the sf bit in the status register is allowed to generate interrupt requests to the cpu. 1 = interrupts from t he ssi module are enabled 0 = interrupts from t he ssi module are disabled se ? ssi enable bit this bit controls whether the ssi is enabled or disabl ed. when the ssi is disabled, the internal counters are reset, the scl clock stops and any transmission in progre ss is aborted. also, t he status register is cleared and the scl and sda pins goes to high impedance. 1 = the ssi module is enabled. thi s bit must be set before any other bits of this register have any effect. 0 = the module is disabled. this is the power-on re set situation. when low, the interface is held in reset but registers can still be accessed. address: $004c bit 7654321bit 0 read: sie se start stop ack schs sr1 sr0 write: reset:00000000 figure 21-3. ssi control register (ssicr) advance information mc68hc908tv24 ? rev. 2.1 314 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) start ? start bit this bit determines if the following byte is going to be preceded by a start signal. this bit is set to init iate a transmissi on or to begin reading data from periphe rals. it also can be se t in the middle of a transmission order to spec ify a repeated start condition. 1 = the following byte will be preceded by a start signal. 0 = a start signal w ill not be produced. stop ? stop bit this bit determines if the next byte is going to be foll owed by a stop signal. this bit is set to finish a transmission or to finish reading data from peripherals. 1 = the next byte will be fo llowed by a stop signal. 0 = a stop signal will not be produced. ack ? acknowledge bit when receiving data, the c pu must write a logic 0 in to this bit so that an acknowledge is generated to the peripheral. when transmitting data, the cpu must write a logic 1 to this bit an d then read it later after the transmission has been completed to know if the peripheral has acknowledged the transfer. schs ? ssi channel select bit this bit controls the mu ltiplexing of the cloc k and data lines to the external pins. 1 = scl2 and sda2 are activated to carr y the ssi signals; scl1 and sda1 goes to high-impedance. 0 = scl1 and sda1 are activated to carr y the ssi signals; scl2 and sda2 goes to high-impedance. note: it is strongly recommended that the last transfer is properly terminated by a stop bit bef ore changing schs. serial synchronous interface module (ssi) registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 315 sr1 and sr0 ? ssi clock rate these bits determine the serial clock frequency as shown in table 21-1 21.6.2 ssi status register sf ? ssi flag bit this read-only bit is set after the oc currence of the ninth falling clock edge and indicates that a complete transfer has occurred. if the sie bit is set, an interrup t will also be gene rated. the scl clock line will stop until the sf flag is cleared, indicating that the cpu has prepared a new byte to transfer or has read the received byte. the sf flag must always be cleared between transfe rs, which can be done in three ways: ? by reading the status register with sf se t, followed by writing or reading the data register ? by a reset ? by disabling the ssi table 21-1. scl rates (hz) at bus frequency sr1 and sr0 2.0 mhz 4.0 mhz 8.0 mhz 00 15.625 k 31.25 k 62.5 k 01 31.25 k 62.5 k 125 k 10 62.5 k 125 k 250 k 11 125 k 250 k 500 k address: $004d bit 7654321bit 0 read: sf dcol 000000 write: reset:00000000 = unimplemented figure 21-4. ssi status register (ssisr) advance information mc68hc908tv24 ? rev. 2.1 316 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) note: if the sf flag is cleared by resetti ng or disabling the ssi before issuing a stop bit, the slave device may enter into an indeterminate state. the first method of clearing sf is always the best. dcol ? data collision bit this is a read-only status bit that indicates an invalid access to the data has been made. an invalid access is: ? an access to the data register in the middle of a transfer, after the first falling edge of scl and before sf is set ? an access to the data register before an access to the status register, after sf is set dcol is cleared by readi ng the status register with sf set, followed by a read or write of the data register. 21.6.3 ssi data register da7?da0 ? ssi data bits these bits are the eight data bits that have bee n received or are to be transferred by the ssi. these bits are not double-buffered but writes to this register are masked duri ng transfers and will not destroy the previous contents. a tr ansfer is triggered by a read to the status register (if sf is set) followed by a write to the data register. during a transfer, the contents of the data regi ster plus the ack bit are shifted (msb first) to the data line (see figure 21-1 ). the signal on the data line, resulting from t he wired-and logic, will be shifted back to the register via least signifi cant bit. at the end of the transfer, the contents of the data register and the ack bit of the contro l register reflect what address: $004e bit 7654321bit 0 read: da7 da6 da5 da4 da3 da2 da1 da0 write: reset:00000000 figure 21-5. ssi data register (ssidr) serial synchronous interface module (ssi) low-power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor serial synchronous interface module (ssi) 317 was present in the exte rnal bus. in that way, the cpu can read the data register and the ack bit to find out the contents of the bus during the transfer. 21.7 low-power modes in wait mode or stop m ode, the ssi halts operat ion. pins sda1, scl1, sda2, and scl2 will main tain their states. if the ssi is nearing completion of a transfer when wait mode or stop mode is entered, it is possible for the ssi to generate an interrupt request and thus cause t he processor to exit wait mode or stop mode immediately. to prevent this occurr ence, the programmer should ensure that all transfers are co mplete before entering wa it mode or stop mode. 21.8 interrupt the ssi has one source of interrupt, the sf fl ag in the ssi status register. this interrupt is enabled by bit sie in the ssi control register. this interrupt will cause the cpu to vector to the address stored in $ffea?$ffeb. advance information mc68hc908tv24 ? rev. 2.1 318 serial synchronous interface module (ssi) freescale semiconductor serial synchronous interface module (ssi) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timebase module (tbm) 319 advance information ? mc68hc908tv24 section 22. timebase module (tbm) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 22.5 timebase register description. . . . . . . . . . . . . . . . . . . . . . . . 321 22.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 22.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 22.2 introduction this section describes the tim ebase module (tbm ). the tbm will generate periodic interrupts at user selectable rates using a counter clocked by the external crystal clo ck. this tbm version uses 15 divider stages, eight of whic h are user selectable. 22.3 features features of the tbm module include: software programmable 1-hz, 4-hz, 16-hz, 256-hz, 512-hz, 1024-hz, 2048-hz, and 4096-hz periodi c interrupt using external 32.768-khz crystal advance information mc68hc908tv24 ? rev. 2.1 320 timebase module (tbm) freescale semiconductor timebase module (tbm) 22.4 functional description note: this module is designed for a 32.768-khz oscillator. this module can generate a periodic interrupt by dividing the crystal frequency, cgmxclk. the c ounter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 22-1 , starts counting when the tbon bit is set. when the counter overflows at the tap selected by tbr2:tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. the tbif flag is cleared by writing a 1 to the tack bit. the first time the tbif flag is set after enabling the timebase module, the interrupt is generated at approximately half of t he overflow period. subsequent events oc cur at the exact period. figure 22-1. timebase block diagram 2 2 2 2 2 2 2 2 2 2 2 2 2 2 128 32,768 8192 2048 cgmxclk sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbmint tbon 2 r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 64 32 16 8 timebase module (tbm) timebase register description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timebase module (tbm) 321 22.5 timebase register description the timebase has one regi ster, the tbcr, which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag bit this read-only flag bit is set when the timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending tbr2:tbr0 ? timebase rate selection bit these read/write bits are used to select the rate of timebase interrupts as shown in table 22-1 . address: $001a bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon tbtst * write: tack reset:00000000 = unimplemented * ptm test mode figure 22-2. timebase cont rol register (tbcr) table 22-1. timebase rate se lection for osc1 = 32.768 khz tbr2 tbr1 tbr0 divider timebase interrupt rate hz ms 0 0 0 32,768 1 1000 0018192 4 250 0 1 0 2048 16 62.5 0 1 1 128 256 ~ 3.9 100 64 512 ~2 101 32 1024 ~1 110 16 2048 ~0.5 1 1 1 8 4096 ~0.24 advance information mc68hc908tv24 ? rev. 2.1 322 timebase module (tbm) freescale semiconductor timebase module (tbm) note: do not change tbr2?t br0 bits while th e timebase is enabled (tbon = 1). tack? timebase acknowledge bit the tack bit is a write-on ly bit and always reads as 0. writing a logic 1 to this bit clears tbif, the timebas e interrupt flag bit. writing a logic 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled bit this read/write bi t enables the timebase inte rrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt enabled 0 = timebase interrupt disabled tbon ? timebase enabled bit this read/write bit enables the timebase . timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialize d by clearing and then se tting this bit. reset clears the tbon bit. 1 = timebase enabled 0 = timebase disabled and the counter initialized to 0s 22.6 interrupts the timebase module can interrupt the cpu on a regular basis with a rate defined by tbr2:t br0. when the timebas e counter chain rolls over, the tbif flag is se t. if the tbie bit is set, enabling the timebase interrupt, the counter chain overflow will gene rate a cpu interrupt request. interrupts must be acknowledged by writing a logic 1 to the tack bit. timebase module (tbm) low-power modes mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timebase module (tbm) 323 22.7 low-power modes the timebase module remains active af ter execution of wait or stop instructions. in wait or stop modes, the timebase register is not accessible by the cpu. if the timebase functions are not required during wait and stop modes, reduce the power consumption by stopping the timebase before enabling the wait or stop instruction. advance information mc68hc908tv24 ? rev. 2.1 324 timebase module (tbm) freescale semiconductor timebase module (tbm) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 325 advance information ? mc68hc908tv24 section 23. timer interface module (tim) 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 23.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 23.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 23.4.4 unbuffered output com pare . . . . . . . . . . . . . . . . . . . . . . .330 23.4.5 buffered output compar e . . . . . . . . . . . . . . . . . . . . . . . . . 330 23.4.6 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 331 23.4.7 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . 332 23.4.8 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . 333 23.4.9 pwm initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 23.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 23.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 23.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 23.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 336 23.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 23.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 23.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 337 23.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 23.9.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 341 23.9.4 tim channel status and control registers . . . . . . . . . . . . 342 23.9.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 advance information mc68hc908tv24 ? rev. 2.1 326 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.2 introduction this section describes the timer in terface (tim) modul e. the tim is a 2-channel timer that prov ides a timing referenc e with input capture, output compare, and pulse-wid th-modulation functions. figure 23-1 is a block diagram of the tim. 23.3 features features of the tim include: two input capture/ou tput compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width-modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits 23.4 functional description figure 23-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programm able independently as input capture or out put compare channels. timer interface module (tim) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 327 figure 23-1. tim block diagram prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a output tof toie inter- 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a logic rupt logic inter- rupt logic output logic inter- rupt logic tclk tch0 tch1 advance information mc68hc908tv24 ? rev. 2.1 328 timer interface module (tim) freescale semiconductor timer interface module (tim) figure 23-2 summarizes the timer registers. addr.register name bit 7654321bit 0 $000f timer status and control register (tsc) see page 337. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0010 timer counter register high (tcnth) see page 340. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0011 timer counter register low (tcntl) see page 340. read: bit 7 654321bit 0 write: reset:00000000 $0012 timer counter modulo register high (tmodh) see page 341. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0013 timer counter modulo register low (tmodl) see page 341. read: bit 7654321bit 0 write: reset:11111111 $0014 timer channel 0 status and control register (tsc0) see page 342. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0015 timer channel 0 register high (tch0h) see page 346. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0016 timer channel 0 register low (tch0l) see page 346. read: bit 7654321bit 0 write: reset: indeterminate after reset $0017 timer channel 1 status and control register (tsc1) see page 346. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 23-2. tim i/o regist er summary (sheet 1 of 2) timer interface module (tim) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 329 23.4.1 tim counter prescaler the tim clock source can be one of th e seven prescaler outputs or the tim clock pin, tclk. the prescale r generates seven clock rates from the internal bus clock. the prescaler select bits , ps[2:0], in the tim status and control register se lect the tim clock source. 23.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 23.4.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0018 timer channel 1 register high (tch1h) see page 346. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0019 timer channel 1 register low (tch1l) see page 346. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 23-2. tim i/o regist er summary (sheet 2 of 2) advance information mc68hc908tv24 ? rev. 2.1 330 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.4.4 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 23.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable channel x tim overflow interrupts and wr ite the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare in terrupt routine (at t he end of the current pulse) could cause two output com pares to occur in the same counter overflow period. 23.4.5 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. timer interface module (tim) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 331 setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 23.4.6 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 23-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic 1. program the tim to set the pi n if the state of the pwm pulse is logic 0. the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000. see 23.9.1 tim status and control register . advance information mc68hc908tv24 ? rev. 2.1 332 timer interface module (tim) freescale semiconductor timer interface module (tim) figure 23-3. pwm peri od and pulse width the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128/256 or 50 percent. 23.4.7 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 23.4.6 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) functional description mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 333 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 23.4.8 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a gener al-purpose i/o pin. advance information mc68hc908tv24 ? rev. 2.1 334 timer interface module (tim) freescale semiconductor timer interface module (tim) note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. 23.4.9 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter by sett ing the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. see table 23-2 . b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 23-2 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on out put compare prevents reliable 0 percent duty cycle gener ation and removes the ability of the channel to self-correct in the ev ent of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. timer interface module (tim) interrupts mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 335 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100 per cent duty cycle output. (see 23.9.4 tim channel status and c ontrol registers .) 23.5 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter value rolls over to $0000 after matching t he value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim stat us and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e = 1. chxf and ch xie are in the tim channel x status and control register. 23.6 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. advance information mc68hc908tv24 ? rev. 2.1 336 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.6.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 23.6.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 23.7 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see 20.8.3 sim break flag control register . to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. timer interface module (tim) i/o signals mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 337 23.8 i/o signals the three tim pins are the extern al input clock tclk and the two channel i/o pins, tch0 and tch1 . each channel i/o pin is programmable independently as an i nput capture pin or an output compare pin. tch0 can be configur ed as buffered output compare or buffered pwm pin. 23.9 i/o registers these i/o registers control and monitor operati on of the tim: tim status and control register (tsc) tim control registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0, tsc1) tim channel registers (t ch0h:tch0l, tch1h:tch1l) 23.9.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock advance information mc68hc908tv24 ? rev. 2.1 338 timer interface module (tim) freescale semiconductor timer interface module (tim) tof ? tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo va lue programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clear ing sequence is complete, then writing logic 0 to tof has no ef fect. therefore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. address: $000f bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 23-4. tim st atus and control register (tsc) timer interface module (tim) i/o registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 339 trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is reset and always r eads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps2?ps0 ? prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the i nput to the tim counter as table 23-1 shows. reset clears the ps[2:0] bits. table 23-1. pres caler selection ps2?ps0 tim clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 not available advance information mc68hc908tv24 ? rev. 2.1 340 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.9.2 tim counter registers the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if tcnth is read during a break inte rrupt, be sure to unlatch tcntl by reading tcntl before ex iting the break interrupt. otherwise, tcntl retains the value latc hed during the break. address: $0010 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 23-5. tim counter register high (tcnth) address: $0011 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 23-6. tim counter register low (tcntl) timer interface module (tim) i/o registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 341 23.9.3 tim counter modulo registers the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clo ck. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim c ounter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: $0012 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 23-7. tim counter mo dulo register high (tmodh) address: $0013 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 23-8. tim counter m odulo register low (tmodl) advance information mc68hc908tv24 ? rev. 2.1 342 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.9.4 tim channel status and control registers each of the tim channel st atus and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 100 percent pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $0014 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 23-9. tim channel 0 stat us and control register (tsc0) address: $0017 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 23-10. tim channel 1 stat us and control register (tsc1) timer interface module (tim) i/o registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 343 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enabl es tim cpu interrupt s on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and renders pin tch1 inoperable. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered output compare/pwm operation. see table 23-2 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation advance information mc68hc908tv24 ? rev. 2.1 344 timer interface module (tim) freescale semiconductor timer interface module (tim) when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin once pwm or output compare operation is enabled. see table 23-2 . reset clears this bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. table 23-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. table 23-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset initial output level high x1 00 initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare timer interface module (tim) i/o registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 345 tovx ? toggle on overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not t oggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 23-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 23-11. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare advance information mc68hc908tv24 ? rev. 2.1 346 timer interface module (tim) freescale semiconductor timer interface module (tim) 23.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: $0015 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 23-12. tim channel 0 register high (tch0h) address: $0016 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 23-13. tim channel 0 register low (tch0l) timer interface module (tim) i/o registers mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor timer interface module (tim) 347 address: $0018 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 23-14. tim channel 1 register high (tch1h) address: $0019 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 23-15. tim channel 1 register low (tch1l) advance information mc68hc908tv24 ? rev. 2.1 348 timer interface module (tim) freescale semiconductor timer interface module (tim) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor rom version overview (rom) 349 advance information ? mc68hc908tv24 section 24. rom version overview (rom) 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.3 flash for rom substitution . . . . . . . . . . . . . . . . . . . . . . . . . 349 24.4 configuration register programming . . . . . . . . . . . . . . . . . . . 351 24.2 introduction this section describes the differences bet ween the rom version (mc68hc08tv24) and the flash version (mc68hc 908tv24) of the microcontroller. basically, the differences are: use of rom instead of flash in both osd and user memories configuration register not programmable on rom version 24.3 flash for rom substitution figure 24-1 shows the structure of mc 68hc08tv24. flash memories and related supporti ng modules are replaced by rom memories. user flash vector space is substituted by rom vector space. additionally, the following regist ers are not present in the rom version: user flash test cont rol register (fl1tcr) user flash control register (fl1cr) osd flash test cont rol register (fl2tcr) osd flash control register (fl2cr) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor rom version overview (rom) 350 rom version overview (rom) flash for rom substitution figure 24-1. mc68h c08tv24 block diagram ptc system integration module on-screen display module break module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user rom ? 24,576 bytes user ram ? 608 bytes monitor rom ? 240 bytes user rom vector space ? 22 bytes single external irq module power pta ddra internal bus rst irq pta7?pta0 timer interface module data slicer module video 4-bit analog-to-digital converter module adcin tch1 tch0 tclk vsync hsync osdpmp scl1 sda1 sda2 v dd v ss v ddcgm v sscgm v ddosd v ssosd r, g, b, i, fbkg serial synchronous interface module scl2 osdvco clock generator module osc1 osc2 cgmxfc 32-khz oscillator phase-locked loop timebase module ptb ddrb ptb7?ptb0 ddrc ptc4?ptc0 osd rom ? 6,656 bytes configuration register security module rom version overview (rom) configuration register programming mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor rom version overview (rom) 351 user flash block protect register (fl1bpr) osd flash block prot ect register (fl2bpr) because of modularity r easons, the osd rom size is 6,656 bytes, but only 6,528 bytes wil l be used by the osd module. the remaining bytes can be programmed with any value. 24.4 configuration register programming the configuration register (config) is not pr ogrammable in the rom version. while in the flash version, the config register can be written once after each reset; in the rom version, the options have to be specified beforehand and delivered to mask elabor ation together with the rom contents. some modules affected by the conf iguration register bits make reference to defaul t values of these bits and have recommendation notes on programming t hem. these notes are not en tirely applicable to the rom version. the conf ig bits will neither assume the described default values after reset nor be m odified later under us er code control. advance information mc68hc908tv24 ? rev. 2.1 352 rom version overview (rom) freescale semiconductor rom version overview (rom) mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor preliminary electrical specifications 353 advance information ? mc68hc908tv24 section 25. preliminary electrical specifications 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 25.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 354 25.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 355 25.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 25.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 356 25.7 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 25.8 adc4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 25.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 359 25.10 clock generation module characteristics . . . . . . . . . . . . . . . 359 25.10.1 cgm component specifications . . . . . . . . . . . . . . . . . . . . 359 25.10.2 cgm electrical specif ications . . . . . . . . . . . . . . . . . . . . . . 360 25.11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 25.12 5.0-v ssi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 25.2 introduction this section contains electrical and timing specifications. these values are design targets and have not yet been fully tested. advance information mc68hc908tv24 ? rev. 2.1 354 preliminary electrical specifications freescale semiconductor preliminary electrical specifications 25.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. the mcu contains circuitry to pr otect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guar anteed to operate properly at the maximum ratings. refer to 25.6 5.0-v dc electri cal characteristics for guaranteed operating conditions. characteristic (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd ?0.3 to + 6.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v maximum current per pin excluding v dd and v ss i 25 ma maximum current into v dd i mvdd 100 ma maximum current out of v ss i mvss 100 ma storage temperature t stg ?55 to +150 c note: preliminary electrical specifications functional operating range mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor preliminary electrical specifications 355 25.4 functional operating range 25.5 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to +85 c operating voltage range v dd 5.0 10% v characteristic symbol value unit thermal resistance tqfp (52-pin) ja 70 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the devic e. k can be determined for a known, t a , and mea- sured p d . with this value of k, p d and t j can be determined for any value of t a . k p j x (t a + 273 c ) + p d 2 ja w / c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 125 c notes: advance information mc68hc908tv24 ? rev. 2.1 356 preliminary electrical specifications freescale semiconductor preliminary electrical specifications 25.6 5.0-v dc electr ical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all ports, r, g, b, i, fbkg, tch0, tch1 (i load = ?5.0 ma) all ports, r, g, b, i, fbkg, tch0, tch1 v oh v oh v dd ? 0.8 v dd ? 1.5 ? ? ? ? v v output low voltage (i load = 1.6 ma) all ports, rst , r, g, b, i, fbkg, tch0, tch1, scl1, scl2, sda1, sda2 (i load = 10 ma) all ports, rst , r, g, b, i, fbkg, tch0, tch1, scl1, scl2, sda1, sda2 v ol v ol ? ? ? ? 0.4 1.5 v v input high voltage all ports, rst , irq , vsync, hsync, scl1, scl2, sda1, sda2, tclk, tch0, tch1 v ih 0.7 x v dd ? v dd v input low voltage all ports, rst , irq , vsync, hsync, scl1, scl2, sda1, sda2, tclk, tch0, tch1 v il v ss ? 0.2 x v dd v v dd supply current run (3) wait (4) stop (5) 25 c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) i dd ? ? ? ? ? ? ? ? ? 5 20 300 50 500 30 12 ? ? ? ? ? ma ma a a a a a i/o ports hi-z leakage current i il ?? 10 a input current i in ??1 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd +2.5 ?9v low-voltage inhibit, trip falling voltage ? lvi5or3 = 1 v tripf 4.13 4.3 4.35 v low-voltage inhibit, trip rising voltage ? lvi5or3 = 1 v tripr 4.23 4.4 4.45 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) ? lvi5or3 = 1 v hys ?100?mv preliminary electrical specifications 5.0-v dc electrical characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor preliminary electrical specifications 357 low-voltage inhibit, trip falling voltage ? lvi5or3 = 0 v tripf 2.5 2.6 2.63 v low-voltage inhibit, trip rising voltage ? lvi5or3 = 0 v tripr 2.6 2.66 2.73 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) ? lvi5or3 = 0 v hys ?60?mv por rearm voltage (7) v por 0 ? 100 mv por reset voltage (8) v porrst 0 700 800 mv por rise time ramp rate (9) r por 0.035 ? ? v/ms notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measurem ents at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd is measured with osc1 = v ss . 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all inputs configured as inputs. 7. maximum is highest voltage that por is guaranteed. 8. maximum is highest voltage that por is possible. 9. if minimum v dd is not reached before the intern al por reset is released, rst must be driven low externally until min- imum v dd is reached. characteristic (1) symbol min typ (2) max unit advance information mc68hc908tv24 ? rev. 2.1 358 preliminary electrical specifications freescale semiconductor preliminary electrical specifications 25.7 5.0-v control timing characteristic (1) 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless otherwise noted symbol min max unit frequency of operation (2) crystal option external clock option (3) 2. see 25.10 clock generation module characteristics for more information. 3. no more than 10% duty cycle deviation from 50% f osc 32 dc (4) 4. some modules may require a minimum freq uency greater than dc for proper operation. see appropriate table for this information. 100 32.8 khz mhz internal operating frequency f op ?8.2mhz internal clock period (1/f op )t cyc 122 ? ns reset input pulse width low (5) 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ? ns irq interrupt pulse width low (6) (edge-triggered) 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 50 ? ns irq interrupt pulse period t ilil tbd note 8 ? t cyc 16-bit timer (7) input capture pulse width input capture period 7. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. 8. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the interrupt service routine plus t cyc . t th, t tl t tltl tbd note 8 ? ? ns t cyc notes: preliminary electrical specifications adc4 characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor preliminary electrical specifications 359 25.8 adc4 characteristics 25.9 timer interface module characteristics 25.10 clock generation module characteristics 25.10.1 cgm component specifications characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v ddosd = 5.0 vdc 10%, v ssosd = 0 vdc symbol min max unit input voltages v adin 0 v dd v d/a resolution b da 44bits d/a conversion error a da ? 1/2 lsb d/a conversion range r da 0 v dd v comparator conversion time t conv 23 t cyc comparator initialization time t ads ?1.3 s notes: characteristic symbol min max unit input capture pulse width t tih , t til 1? t cyc characteristic symbol min typ max unit crystal reference frequency (1) 1. fundamental mode crystals only f xclk 30 32.768 100 khz crystal load capacitance (2) 2. consult crystal manufacturer?s data. c l ???pf crystal fixed capacitance (2) c 1 6 2 c l 40 pf crystal tuning capacitance (2) c 2 6 2 c l 40 pf feedback bias resistor r b 10 10 22 m ? series resistor r s 330 330 470 k ? notes: advance information mc68hc908tv24 ? rev. 2.1 360 preliminary electrical specifications freescale semiconductor preliminary electrical specifications 25.10.2 cgm electrical specifications description symbol min typ max unit operating voltage v dd 2.7 ? 5.5 v operating temperature t ?40 25 130 o c crystal reference frequency f rclk 30 32.768 100 khz range nominal multiplier f nom ? 38.4 ? khz vco center-of-range frequency (1) 1. 5.0 v 10% v dd f vrs 38.4 k ? 40.0 m hz medium-voltage vco center-of-range frequency (2) 2. 3.0 v 10% v dd f vrs 38.4 k ? 40.0 m hz vco range linear range multiplier l 1 ? 255 vco power-of-two range multiplier 2 e 1?4 vco multiply factor n 1 ? 4095 vco prescale multiplier 2 p 118 reference divider factor r 1 1 15 vco operating frequency f vclk 38.4 k ? 40.0 m hz bus operating frequency (1) f bus ??8.2mhz bus frequency @ medium voltage (2) f bus ??4.1mhz manual acquisition time t lock ??50ms automatic lock time t lock ??50ms pll jitter (3) 3. deviation of average bus frequency over 2 ms. n = vco multiplier. f j 0? f rclk x 0.025% x 2 p n/4 hz external clock input frequency pll disabled f osc dc ? 32.8 m hz external clock input frequency pll enabled f osc 30 k ? 1.5 m hz notes: preliminary electrical specifications memory characteristics mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor preliminary electrical specifications 361 25.11 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash pages per row (both flash memories) ? 8 pages flash bytes per page (user flash) ? 8 bytes flash bytes per page (osd flash) ? 4 bytes flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32 k ? 8.4 m hz flash charge pump clock frequency (see 12.5.1 flash charge pump frequency control .) f pump (2) 2. f pump is defined as the charge pump clock frequency re quired for program, erase, and margin read operations. 1.8 ? 2.5 mhz flash block/bulk erase time t erase 100 ? ? ms flash high-voltage kill time t kill 200 ? ? s flash return to read time t hvd 50 ? ? s flash page program pulses fls pulses (3) 3. fls pulses is defined as the number of pulses used to program the flash using the required smart program algorithm. 1 20 tbd pulses flash page program step size t prog (4) 4. t prog is defined as the amount of time during one page program cycle that hven is held high. 1.0 ? 1.2 ms flash cumulative program time per row between erase cycles t row (5) 5. t row is defined as the cumulative time a row can see the program voltage before the row must be erased before further programming. ??tbdms flash hven low to margin high time t hvtv 50 ? ? s flash margin high to pgm low time t vtp 150 ? ? s flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 100 ? ? cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 100 ? ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the en tire temperature range for at least the minimum time specified. ? 10 ? ? years notes: advance information mc68hc908tv24 ? rev. 2.1 362 preliminary electrical specifications freescale semiconductor preliminary electrical specifications 25.12 5.0-v ssi characteristics figure 25-1. ssi timing characteristic diagram symbol (1) 1. these signals are open-drain type outpu ts. the time required for these signals to attain steady high or low state is de- pendent on the external signal capaci tance and pull-up resistor values. min (2) 2. all these values do not depend on output clock (scl) selected frequency. the internal bus clock frequency used is 8mhz. typ max unit start condition setup time m1 4.7 ?? ms start condition hold time m2 4.0 ?? ms data hold time m3 125 ?? ns data falling from ninth clock falling (3) 3. m4 and m5 are not part of the i 2 c standard. m4 4.0 ?? ms clock rising from data falling (3) m5 4.0 ?? ms stop condition setup time m6 4.0 ?? ms bus free time between a stop and a start condition m7 4.7 ?? ms notes: m1 scl m5 sda m3 m6 start m7 ack stop start scl m2 sda m1 ack start repeated m2 m4 mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor mechanical specifications 363 advance information ? mc68hc908tv24 section 26. mechanical specifications 26.1 contents 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 26.3 52-pin plastic quad flat pack (pqfp). . . . . . . . . . . . . . . . . . 364 26.2 introduction this section gives the di mensions for the 52-pi n thin quad flat pack (case 848d-03). the following figure shows the latest package drawi ng at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow worldwide web on- line instructions to retrieve the current mechanical specifications. advance information mc68hc908tv24 ? rev. 2.1 364 mechanical specifications freescale semiconductor mechanical specifications 26.3 52-pin plastic quad flat pack (pqfp) -t- m y e w c -h- datum plane view p 0.01 (0.004) 52 1 40 39 14 26 27 view y -n- -l- a s l-m m 0.20 (0.008) n s h s l-m m 0.20 (0.008) n s t 0.05 (0.002) l-m s b v -m- g 48x pin 1 ident s l-m m 0.20 (0.008) n s h 0.05 (0.002) n s l-m m 0.20 (0.008) n s t s l-m m 0.13 (0.005) n s t f b1 section j1-j1 j d base metal plating 44 pl -l-, -m-, -n- j1 j1 g view y 3 pl notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -l-, -m- and -n- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -t-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.46 (0.018). minimum dimension between protrusion q1 -h- datum plane r2 k a1 c1 view p dim min max min max inches millimeters a b c 1.70 0.067 d 0.20 0.40 0.008 0.016 e 1.30 1.50 0.051 0.059 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.026 bsc j 0.07 0.20 0.003 0.008 k m s v w 0.05 0.20 0.002 0.008 y a1 0.20 ref 0.16 0.008 ref 0.006 b1 c1 1.00 ref 0.039 ref r1 r2 0 0 1 2 0.09 0.004 0.08 0.20 0.003 0.008 0.08 0.20 0.003 0.008 q q 0 7 0 7 r1 q2 13 10.00 bsc 10.00 bsc 0.394 bsc 0.394 bsc 0.50 ref 0.020 ref 12 ref 12 ref 12.00 bsc 0.472 bsc 12.00 bsc 0.472 bsc 12 ref 12 ref and adjacent lead or protrusion 0.07 (0.003). mc68hc908tv24 ? rev. 2.1 advance information freescale semiconductor ordering information 365 advance information ? mc68hc908tv24 section 27. ordering information 27.1 contents 27.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 27.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 27.2 introduction this section contains ordering numbers for the mc68hc908tv24 and the mc68hc08tv24. 27.3 mc order numbers table 27-1. mc order numbers mc order number (1) 1. fb = plastic quad flat pack operating temperature range MC68HC08TV24CFB ?40 c to +85 c mc68hc908tv24cfb ?40 c to +85 c note: advance information mc68hc908tv24 ? rev. 2.1 366 ordering information freescale semiconductor ordering information how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 2.1 mc68hc908tv24/d august 16, 2005 |
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